The days of massive ASIC volumes are over, according to Dr Naveed Sherwani, CEO of Open Silicon.
“The days of one chip with humongous volume are gone”, Sherwani told the recent Globalpress Summit Conference, “now we have one chip with derivatives. A platform is created, and a bunch of derivatives is made from the platform which have 80-90% of the characteristics of the platform with a small change.”
“If we do very low cost we generally do derivatives,” added Sherwani, “give me your platform chip and I can do derivatives at very low cost.”
“From the moment the design is finalised we make a prediction about the delivery date plus or minus one week”, said Sherwani, “our success rate is currently 83% and as been as high as 92% because 40nm and 28nm has been unpredictable.”
Sherwani wrote the standard text book for EDA, called ‘Algorithms for VLSI Physical Design Automation', and headed up Intel’s last attempt on the ASIC market before founding Open-Silicon in 2003.
Open-Silicon prides on making silicon accessible to people who are not silicon-savvy.
“We have done a chip from a four page description in English by a manager who was not an engineer”, added Sherwani, “we wrote a technical specification of what he wanted.”
“People don’t believe that there’s an ASIC company that can receive a spec from you written on a napkin and take it all the way to silicon” said Sherwani, “most companies want RTL or a Net List, but all that our customers need is the money.”
The ASIC industry is holding up well against the competition of FPGAs which have, as a product sector, stopped growing.
“There are two to three thousand ASIC starts every year, and 85,000 FPGA starts”, said Sherwani, “but the FPGA business is not going to grow unless they can offer FPGA at ASIC prices. And they can’t do that because FPGA is such an inefficient use of silicon.”