Guest columnist Jim Gillberg, director of automotive applications at Fairchild Semiconductor describes approaches for combining power and control in a single package
Even before the first transistor was invented, there has been a constant drive to integrate more functionality into a single product.
In IC design, this constant need for higher integration has been achieved through constant improvements in the photolithography used to fabricate the devices.
There has been a similar drive for smaller, less costly and higher performance power devices. However advancements in the RDS(ON) (on resistance) of the power devices while taking advantage of improved photolithography has been enabled by new and more complex structures.
The current power MOS devices developed do not use the traditional planar topologies that had been used for many years.
They have been replaced with much more complex trench or charge-balanced technologies. Both of these approaches add process complexity to significantly lower the specific on resistance of a given mosfet as compared to the older planar technologies.
As system complexity grows, it becomes natural to want to combine both higher performance mixed signal IC functions with high power silicon switches.
However, when you look at the process complexity required for combining high performance mixed signal control with power handling capability, it quickly becomes obvious there has to be a better way than to just integrate everything into a complex single piece of silicon.
In addition to the process complexity, one major drawback is for the high performance vertical DMOS or other power structures, the back side of the die is the drain (or collector) of the power device with current flowing vertically through the die.
In contrast, most mixed-signal ICs have a P-substrate material where the back of the wafer can serve as a system ground.
Following is an example of a complex high power automotive solenoid driver. Two different approaches were taken.
The first combines the high power switch with the high performance control block into one piece of silicon. The other is an example of how using advanced package and isolation techniques can reduce the cost of a product.
A series of generic assumptions were made on the silicon cost of each product to obtain a comparison of the two approaches: vertical DMOS 6-inch wafer 9 masking levels at $30/level; high voltage BCD DLM process with 24 masking layers at $30/level.
As each die can have a process optimised for signal or power, the actual silicon area for the multiple die approach is about 60% of the single die.
Using the assumptions above generates a cost estimate of $1.00 for the single IC and about $0.40 for the multiple die.
One of the major issues that must be over come when combining power and control in a single package is that the back of the power device is normally the drain or collector of the power switch, so the control die must be electrically isolated from the die attach area that the power die is mounted on.
There are several ways to approach the electrical isolation required between the power and control devices:
1) Separate the die attach areas
2) Use non conducting epoxy for the control die
3) Use polyimide laminate or tape die attach for the control die
In the example above, two types of isolation are used. There are three separate die attach areas in the package. Each of these die attach areas can have a different electrical potential. On the left and right die attach areas, the power device is soldered to the paddle while the control IC uses a polyimide laminate that electrically isolates the die from the paddle.
Each technique for isolation has its advantages and disadvantages with regards to cost, reliability and manufacturability.
Some packages like the MLP or PQFN devices (similar to the package shown in Figure 1) can easily accommodate multiple die attach areas. But traditional power packaging such as the TO220 or TO252 - which have a thick header or tab - are not easily divided into two separate electrical areas.
As we continue to follow the inevitable path of higher level integration and more “systems on a chip” and we begin to mix high power capabilities into these systems, you will find more often than not the product you are evaluating actually has several silicon die molded into it.
See also on our website
TI puts two power mosfets in one package
Fairchild and Infineon agree standard pin-out for mosfets