Digital system chips can now be designed entirely in ANSI C++, claims Mentor Graphics, following the release of extensions to its Catapult tool.
"You can now synthesize from C everything that can be synthesised by RTL synthesis tools to make gates," Mentor high-level synthesis director Shawn McCloud told Electronics Weekly.
Prior to this release, said McCloud, certain digital functions, dubbed 'reactive inter-block control logic' by Mentor, have been unsynthesisable and have had to be hand developed in RTL.
To get over this hurdle, the firm has developed a C class that gives the tool enough information to automate the synthesis of reactive inter-block control logic.
"By giving designers a new class that allows them to code in the C source description the specific behaviour, we have opened the design scope to specify asynchronous data communication and include reactive systems such as arbiters, memory controls, bus interfaces, cache units, and dispatchers," claimed McCloud.
Along with the reactive control logic extension comes additions for back-annotation and power reduction.
Until now, said McCloud, issues identified when testing at the RTL level had to be addressed at the RTL level. "We have come up with a mechanism to back-annotate the RTL behaviours into the C source," he said. "It has been very easy to generate RTL that you cannot verify."
According to McCloud, the most common way of reducing power in logic chips at the moment is clock gating, but deciding which clocks get gated is all done by hand.
"An expert makes decisions that these registers do not need to be toggled at this time and declares this block as a clock-gating candidate," he said. "Whether these are then selected for clock gating is decided during back-end synthesis."
Now, he claims, Catapult can do this. "What is novel here is that with high-level synthesis we are able to get to perfect clock gating where every single register than could be gated has been identified as a gating candidate," claimed McCloud.
This ability has also been extended to power-line gating.