I look forward to the emancipation of FPGAs, writes Douglas Hunter, marketing v-p at Lattice Semiconductor
The end of 2011 marks as well the end of any remaining debate about the emergence of programmable logic, and, in particular, FPGAs. In fact, FPGAs have more than emerged: driven by new markets and applications for low cost, high volume devices, FPGAs have been emancipated.
No longer are they confined to markets that could tolerate their high cost and high power consumption. Rather, a new breed of innovative, low cost and low power devices – “mid-range” FPGAs – is fueling the broad and rapid adoption of FPGAs, at the expense of both customised Asics and inflexible ASSPs.
Mid-range FPGAs typically span a density range from 10K to 250K LUTs, and increasingly are being used in applications where previously only high end, expensive FPGAs could be used.
While there will continue to be a place for high end FPGAs, most of the market neither needs nor benefits from ultra-high density FPGAs built on the most advanced process node and running the fastest SerDes.
Our recently announced mid-range LatticeECP4FPGA family, for example, offers the majority of customers the advanced features they need (deep memories, hardened IP, fast SerDes, powerful DSP capabilities, high speed I/O) without the cost and power burden of the non-essential, high-end features that they were formerly forced to pay for.
While consumer products comprise one of the most obvious markets for high volume, low cost FPGAs, the demand for lower cost and lower power FPGAs is growing within the traditional markets for programmable logic as well, including wireless applications such as base station remote radio heads. Other emerging markets that are embracing mid-range FPGAs include security/surveillance and video displays.
With mid-range FPGAs now delivering not only low cost and low power but exceptional performance, the markets for these devices will continue to expand, even as the high end market compresses.
The emancipation of FPGAs has implications as well for how and when smaller process nodes are implemented. While there is no question that the overall trend, driven by customer need, will be to smaller nodes, the race to those technologies may well slow as it becomes clear that smaller process nodes do not automatically result in lower power or lower cost.
In fact, our 65nm FPGA is up to half the price and power of competitive 40nm, and even 28nm, FPGAs. Just as most of the market has no need for very high density devices, so too does it not need smaller process nodes unless they deliver a clear customer benefit.