Cavium Networks has announced a new version of its Octeon internet application processor (IAP) family based on multi-core MIPS64 processors.
The second generation processor is designed to offer x4 performance of the first generation processor.
According to Cavium, over the past two years, general-purpose multi-core processors have become mainstream in embedded, networking, wireless, storage and high-bandwidth broadband applications.
“All major Tier-1 OEMs in the market have adopted multi-core processors and ported millions of lines-of-code of software, including proprietary operating systems, to achieve unprecedented gains in performance, power and cost savings,” said the processor company.
The architecture integrates 1 to 32 custom cnMIPS64 cores and up to 75 application acceleration engines for QoS, packet processing, TCP, compression, encryption, RAID and de-duplication.
Octeon II features a new Hyperconnect crossbar with low-latency and virtualisation features, up to 400Gbit/s of DDR3 memory bandwidth, up to 100Gbit/s of network connectivity, said Cavium.
I/Os include gigabit Ethernet, 10 gigabit Ethernet, PCI Express Gen 2, USB2.0, serial Rapid I/O (sRIO) and Interlaken.
The multi-core architecture provides support for standard operating systems, GNU tool-chains, C/C++ based software applications and unique hardware acceleration engines with an advanced multi-core scheduler.
The first system-on-chip implementation, the CN63XX integrates 2 to 6 MIPS64 cores and is targeted telecoms switches and 3G/4G basestations.
Each superscalar, dual-issue MIPS64 R2 core has 37kbyte I-cache, 32kbyte D-cache operating at up to 1.5GHz for up to 9GHz compute cycles along with 2MB of low-latency, feature rich L2 cache.
Cavium Networks is represented in Europe by Ismosys.