The leading semiconductor companies are now undertaking the transition from 90nm to 65nm.
“It’s not going to be easy,” said Wim Roelandts, CEO of Xilinx, which plans its first 65nm products for next year. “Even the shrink is becoming difficult.”
In recent semiconductor process nodes the shrink has been the relatively simple part. The difficult parts have been the integration of new materials, the correlation between design and manufacturing, switching off power to different parts of the chip, the integration of different transistor types and using different oxide thicknesses.
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A 65nm Nfet from IBM
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According to Paul Farrar, v-p for semiconductor process development at IBM, 60 per cent of the benefits gained from 65nm processing are delivered by these innovations in materials and design techniques with only 40 per cent deriving from the direct effect of the shrink.
At Fujitsu Microelectronics, which made 65nm available in September, the process incorporates a range of transistors with different leakage power and performance points, allowing designers to trade off power versus performance.
Xilinx uses three different oxide thicknesses: single thickness for the logic array representing 40 per cent of the chip; double oxide for the configuration transistors; and triple thickness for the I/O. So 60 per cent of the chip does not leak at all.
Freescale Semiconductor is to fab a wireless baseband processor on a 65nm process before the end of the year. “65nm leakage control has been well-mastered for over a year,” said Denis Griot, senior v-p and general manager for EMEA at Freescale.
Three 65nm announcements were made in October. Intel’s CEO Paul Otellini said Intel began shipping 65nm microprocessors in the third quarter, TSMC said it started running multi-project wafers for prototype 65nm ICs, and Texas Instruments’ CEO Rich Templeton who said TI’s 65nm yields are now “very good”.