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Analog Devices has introduced a wideband analogue-to-digital converter (ADC) which it claims does not have the noise-level penalties usually attributed to multi-MHz bandwidth ADCs.
The design is based on a traditional discrete sigma-delta architecture which has been implemented in a continuous-time loop.
The design has a combination of highly over-sampled sigma-delta architecture with a highly noise-shaped design to achieve the 10MHz input bandwidth in a dual channel 16-bit ADC without the expected noise penalty.
Pipeline and SAR ADC architectures are common analogue architectures today. Pipeline ADCs are typically used for wireless infrastructure, video processing and other applications where performance requirements dictate wide bandwidth.
SAR ADCs are usually used for industrial controls and data acquisition systems where precision and low-noise are key performance factors. A gap in the converter space exists today where the application needs of emerging technology simultaneously demand high dynamic range and wide bandwidth.
According to Nitin Sharma, product manager of high speed converters at ADI, the design incorporates a 5th order loop filter and has a 640Msample/s sampling rate.
"This device also has a fixed high impedance input which means that there is no external input buffer which cuts power consumption at the system level," said Sharma.
Another feature of the design is the internal decimation low pass filter and sample rate converter which provides the noise filtering for the sigma-delta architecture.
The 16-bit, AD926x uses principles of over sampling, noise shaping and input characteristics. The quiet resistive input structure relaxes the requirements of the driver amplifier while the higher order over-sampled continuous time loop filter attenuates out-of-band signals reducing the need for large baseband filters and other signal conditioning circuitry.
The highly integrated AD9261 and AD9262 feature an on-chip PLL clock multiplier, decimation filters, and sample rate converters and provide output data rates between 30 MSPS (mega-samples-per-second) and 160 MSPS.
The AD9267, which features only the 640-MSPS modulator core and PLL clock multiplier, presents the high speed data directly to the output. This allows designers to offload signal processing functions to an FPGA or other processor.
The 150-mW per channel to 350-mW per channel power consumption of the new CTSD converters is matched to a range of communications and industrial applications, including emerging radio architectures, such as direct down conversion, where the dual AD9262 and AD9267 can be used to support multiple wireless carriers and standards simultaneously.