Xilinx has updated its FPGA design software with a system that speeds up recompilation of designs.
Making changes to a design’s VHDL or Verilog normally forces the whole design to be recompiled.
“You can make a simple one line change in the HDL, and the ripple effects can be enormous,” Bruce Talley, v-p of Xilinx’s software division, told Electronics Weekly.
Thus the firm worked with EDA firm Synplicity to develop SmartCompile, which has two main components.
“SmartGuide looks at the previous implementation of the design and tries to preserve as much of the placement and routing as it can,” Talley explained.
The system will push placements, but will not affect functionality or timing, claimed the firm.
SmartPartitions goes further, and allows the designer to lock down a section of the design so it is unaffected by any recompilation changes. This guarantees timing is unchanged for that section.
“We simply copy and paste that section of the design,” said Talley.
He said firms that have tested the software have typically set up five to ten partitions in a design, usually those that are timing critical.
“Overall we’re seeing two to six times improvement in incremental compile runtimes,” claimed Talley.
This is across 84 different designs, with an average speed-up of 2.5x.
The new software – ISE v9.1i – has also been modified to improve the initial compile time on large complex designs with tough timing constraints.
A technology dubbed SmartPreview allows the designer to pause a compilation run and see how the system is progressing.
“What SmartPreview does is if you’ve got a long compilation and you’re not sure whether it’s working, you can pause, take and snapshot then stop or resume,” Talley explained.
If it’s not doing well, the designer can go back and specify easier timing constraints.
Dynamic power has also been addressed. “This version of the router is sensitive to capacitance in the routing resources,” said Talley.
“By being aware of capacitance – especially for non timing critical paths – it can choose the right resources for lower power.”
The synthesis tool also works to reduce the number of switching events in logic, which has a direct impact on dynamic power.
www.xilinx.com