Charlie Huang, senior VP and Chief Strategy Officer, Cadence Design Systems talks to Electronics Weekly about important trends in design tool architectures, how EDA is helping tackle complexity in analog and multicore designs, and how the industry is reacting to adapt to the current economic conditions...
1. What are the main issues for designers when choosing an EDA tool chain?
While individual tool capabilities will always be important, design teams are looking for solutions, not disparate collections of point tools. A comprehensive solution for a challenge such as mixed-signal verification or low-power design requires a suite of tightly integrated tools, backed by services and consulting and production-proven methodologies. The EDA tool chain must also provide easy access to the entire ecosystem needed to design a product, including foundries and third-party IP.
While tight integration among a supplier's own tools is crucial, the EDA tool chain must also allow designers to use internally-developed or third-party tools. This requires support for standards such as SystemC, SystemVerilog, and the OpenAccess database.
In these challenging economic times, some design teams will emphasize costs while choosing an EDA tool chain. More important than the cost of purchase is the cost of ownership. An "inexpensive" tool that doesn't fully meet user needs, doesn't fit well into the EDA flow, or is buggy or difficult to learn and use, will end up being very expensive indeed. The real bottom line is how well an EDA tool chain helps a company meet its goals for productivity and profitability. By accelerating time-to-market and enabling high-quality designs, the right EDA tool chain is a key financial asset.
2. Name one important trend in design tool architectures?
One important trend is the need to architect - or re-architect, in many cases - EDA tools to run on multicore platforms. It is very clear that compute platforms going forward will include more and more processor cores. Today PCs and workstations with 2, 4 or 8 cores are commonplace. In the near future, platforms will have 32 or more processor cores, entering the realm of what some call "manycore."
Since future performance increases will come from the use of multiple cores rather than more powerful single processors, EDA tools must take full advantage of multicore platforms in order to provide the performance needed for next-generation IC design. However, most existing EDA applications were built for single processors. Thus, a large amount of legacy code must be parallelized for multicore platforms. This work is well underway at Cadence with both our digital and analog design flows.
3. How is EDA helping tackle complexity in multicore designs?
Chip designs containing multicore processors will challenge design tools on a variety of fronts. Two key challenges involve functional verification and physical and electrical design.
Multicore systems greatly increase the verification task as the potential for bugs skyrockets with the rising number of complex interacting processors, instruction streams, and data flows. Sophisticated bus arbiters, distributed multi-hierarchy memory and processor cores all require thorough verification that is only possible with transaction-level modeling, metric-driven verification, constrained random testing, and hardware acceleration and emulation.
Complex multicore systems also introduce physical and electrical design requirements - such as low-voltage differential signaling connections, crossbar switching architectures, and wide buses that run across chip - that do not easily fit into vanilla standard cell design methodology of the past.
Interestingly, part of the solution to the increased complexity of multicore design is to evolve EDA software to best take advantage of the multicore processing available in modern computers and networks. Cadence took an early lead in multicore EDA by parallelizing both the Cadence Nanoroute Advanced Digital Router and the Virtuoso Space-Based Router several years ago, and applied the lessons learned from that experience to a new generation of EDA tools. More recently, Cadence extended multicore capabilities by parallelizing the entire Encounter Digital Implementation (EDI) System flow and much of the Incisive verification flow.
4. How EDA is helping tackle complexity in analog designs?
One way that Cadence design flows tackle complexity in analog design is by incorporating intelligent editing techniques within the environment to preclude design patterns that would cause problems further downstream in areas such as design rule checking(DRC) or reticle enhancement techniques (RET). This increases productivity and reliability throughout the design flow.
Another feature that addresses complexity is the constraint-driven design flow, which harnesses the environment to enforce custom requirements for a particular design. This technology boosts the efficiency of developing the types of high-quality mixed-signal designs that are in high demand for the consumer electronics market. As with digital, analog complexity creates a big need for verification.
We address the analog verification requirement with different types of simulation - from full Spice to FastMOS - to meet different speed/accuracy needs, as well as the Virtuoso Accelerated Parallel Simulator that applies multicore technology to analog simulation.
5. How is the industry reacting to adapt to the current economic conditions, and what will drive recovery?
Let me speak to how Cadence is adapting to current economic conditions. In 2009, Cadence positioned itself for future growth. Our primary focus was, and continues to be, on improving customer relationships. We want to help advance their business objectives. Our customers are looking for the fastest path to profitability in an increasingly competitive global market and they are looking to EDA for the surest path to design creation, integration and optimization.
We have honed our organization and aligned our R&D program to deliver solutions to our customers that provide them with greater value. In addition to improving our customer engagements, we also strengthened our foundation technology, and reduced our overall cost structure. We have identified new opportunities for growth in mixed-signal design, IP integration and product realization and in 2010, we renewed the Cadence commitment to innovation, quality and accountability.
According to the SIA, the strong focus on inventories throughout the supply chain has mitigated the impact of the worldwide economic downturn and positioned the semiconductor industry for growth as the global economy recovers.
Recovery is being driven by three things: continued expansion in emerging markets such as India and China, technology advances that continue to provide the market with price-conscious products, and rising consumer confidence. We believe that these drivers position the semiconductor industry and EDA for growth in 2010.
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