Renesas Technology has given details of a semiconductor manufacturing technology on a 45nm process for system-on-chip devices and microprocessors at the 2007 Symposium on VLSI Technology being held in Kyoto, Japan.
The 45nm process has a p-type transistor with a titanium nitride (TiN) metal gate and an n-type transistor with a conventional polysilicon gate. It differs from previous generation transistor technology by using a 2-layer gate structure instead of a single-layer gate for better control of the threshold voltage.
Also, the new hybrid structure applies strained-silicon manufacturing techniques to boost current drive capability.
"These innovations produce about a 20 per cent performance improvement compared to the previous hybrid structure. Importantly, the new structure can be fabricated at low cost because it requires no major changes to the current-generation manufacturing process," said the company.
An experimental chip containing transistors with a 40nm gate length has been fabricated. Data from tests performed on this chip have confirmed world top-level drive performance: 1,068 µA/µm for the n-type transistor and 555 µA/µm for the p-type transistor at a 1.2 V power supply voltage.
The first element of the newly developed chip fabrication technology is the new p-type transistor gate structure, which consists of two titanium nitride layers. A high-k layer, CVD-TiN layer, PVD-TiN layer, and polysilicon are stacked on a silicon substrate in that order.
The PVD-TiN layer is denser than the CVD-TiN layer, so silicon diffusion into the CVD-TiN layer from the polysilicon electrode is suppressed, preventing property changes that would otherwise increase the threshold voltage. According to Renesas, the two TiN layers actually lower the transistor's threshold voltage by approximately 100 mV, to a level appropriate to a low-leakage device.
The other element of the newly developed technology is the strained-silicon technique already widely used in cutting-edge semiconductor devices. The strained-silicon technique improves the drive performance in two ways. It distorts a channel part, forming a path through which current flows. It also widens or narrows silicon lattice spacing, enabling electrons and holes to move more easily.