Santa Clara-based Telairity Semiconductor has announced a processor architecture for high definition (HD) video encoding.
“Harnessing multiple independent vector/scalar cores, the multi-core Telairity-1 architecture is specifically designed to handle the computational requirements of the H.264 [MPEG-4 Part 10] HD codec,” said the firm. “An H.264 compression engine requires four to six times the computational power of an MPEG-2 compression engine.”
H.264 offers higher compression ratios than MPEG-2 and is touted as the next standard for professional broadcast use.
Telairity's chip combines five independent vector-scalar cores, a video controller, and a DRAM controller supporting an I/O bandwidth up to 5.3Gbit/s. Each core has four vector pipes with independent hardware, an independent scalar unit, 128kbyte vector SRAM, a 4kbyte vector SRAM data cache, an 8kbyte scalar scratchpad memory, and a 32kbyte instruction cache.
The first chip with this architecture, the T1P2000, will sustain 55.5Goperation/s when clocked at 668.25MHz - nine times the 74.25MHz 20bit video standard - claims the firm.
“Where a general-purpose, 600MHz to 1GHz DSP based real-time H.264 encoder implementation would require 18 to 32 DSPs and six or more FPGAs,” said Telairity, “our solution requires four to eight Telairity video processor chips and one small FPGA to achieve equivalent bit rates.”
Beyond professional broadcast applications, the Telairity-1 processor will be used to enable HD video applications in video conferencing, security and surveillance, and medical imaging systems.
Packaged in a 1,156-pin flip-chip ball grid array, samples of the T1P2000 are available now with production quantities due in the last quarter of this year.
www.telairity.com