Isle of Wight-based DSP specialist
RF Engines (RFEL) has developed a low-resource algorithm for fast vector translation.
Implemented in a Xilinx Virtex 5 FPGA, it executes 350Mconversion/s from 2x20-bit rectangular to 20-bit magnitude, 12-bit angle, polar coordinates.
According to MD John Summers, the conventional algorithm uses 1669 slices - around seven per cent - of an SX35 FPGA, whereas the RFEL version uses only 274 slices.
“By saving this extent of logic, our customer was able to execute their design in one FPGA rather than spreading it over two,” he said.
The penalty is the need for three 36kbit block RAMs and two DSP48 on-chip processors - one and three per cent of each resource respectively.
The customer has an electronic warfare application. “This algorithm lets you characterise a signal when you don’t know what signal you are looking for,” said Summers.