Researchers at Hewlett Packard announced a breakthrough that they said could lead to the creation of field programmable gate arrays (FPGA) up to eight times denser, while using less energy for a given computation than those currently being produced.
In addition, the researchers claimed that such chips could be built using the same sized transistors as those used in today's FPGA design, meaning they could be built in current fabrication facilities with only minor modifications.
The technology calls for a nanoscale crossbar switch structure to be layered on top of conventional CMOS, using an architecture HP Labs researchers have named "field programmable nanowire interconnect” (FPNI), a variation on FPGA technology.
The research, by Greg Snider and Stan Williams of HP Labs, is a featured paper in the January 24 issue of Nanotechnology, a publication of the British Institute of Physics. The research was conducted using classic modelling and simulation techniques, but Williams said HP is working on producing an actual chip using the approach, and could have a laboratory prototype completed within the year.
"As conventional chip electronics continue to shrink, Moore's Law is on a collision course with the laws of physics," said Williams, an HP senior fellow and director of quantum science research at HP Labs, who in July 2005 made headlines for using nano-imprint lithography to make experimental memory chips with 30nm electrical pathways.
"Excessive heating and defective device operation arise at the nanoscale. What we've been able to do is combine conventional CMOS technology with nanoscale switching devices in a hybrid circuit to increase effective transistor density, reduce power dissipation, and dramatically improve tolerance to defective devices," he continued.
In the FPNI approach, all logic operations are performed in the CMOS, whereas most of the signal routing in the circuit is handled by a crossbar that sits above the transistor layer. Because conventional FPGAs use 80 per cent to 90 per cent of their CMOS for signal routing, HP said the FPNI circuit is more efficient since the density of transistors actually used for performing logic is much higher and the amount of electrical power required for signal routing is decreased.
The researchers presented a "conservative" chip model using 15nm wide crossbar wires combined with 45nm half-pitch CMOS, which they said they believe could be technologically viable by 2010.
Snider and Williams also used a model based on 4.5nm wide crossbar wires, which they said could be ready by 2020. The 4.5nm crossbar architecture combined with 45nm CMOS would yield a hybrid FPGA about 4 per cent the size of a 45nm CMOS-only FPGA, they said. In this case, the clock speed will likely decrease, but so will energy per computation.