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DATE: Intel still obeying Moore's Law

Tuesday 17 February 2004 13:08
EW Daily News 17/02/2004 13:08:19 - DATE: Intel still obeying Moore's Law
DATE: Intel still obeying Moore's Law Richard Ball
Intel remains committed to keeping its semiconductor process aligned with Moore's Law, citing extreme UV lithography, novel transistor layouts and new materials as the key factors.
Greg Spirakis, Intel v-p and director of design technology, said: Although there's been much discussion over the demise of Moore's Law, we don't see that happening any time soon.
Spirakis made his comments during his keynote speech to open the Design, Automation and Test (DATE) conference in Paris today.
EUV will open up the feature sizes, he said, adding that three dimensional transistors such as Intel's Trigate design and strained silicon will keep the chip process on track. And high-k gates will address some of the leakage challenges, he said. Future technologies will include carbon naotubes and silicon nanowires.
Demand for transistors will also be maintained, he said, citing the increasing importance of consumer electronics and the continued rise in Internet traffic.
However, he told listeners at the EDA conference that tools much evolve to meet the need for larger devices. We believe the design challenges must be overcome to fully utilise the transistors' capabilities.
There is a need to balance more metrics, he said, not just speed, area and power. Added to these will be manufacturability, reliability and cost.
Spirakis outlined plans for a new level of design abstraction, already tested by Intel, that uses high level models and equivalence checking to design blocks of logic. We need to find a way to dramatically increase the level of design abstraction while maintaining a link to the lower levels of design, he said.
SystemVerilog is a start, he said, the first step in my mind of upping the abstraction level. This can bridge the gap and enable verification.
Intel's new design technique results in models with one-hundredth the number of lines of code compared to register transfer level models. Using equivalence checking and testing the system on existing design allowed the firm to find bugs that had previously passed through the process.
We need to do something we did a decade ago - a dramatic leap in design abstraction, Spirakis added.
 

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