Guest columnist Mark Glasser from Mentor Graphics believes that Open Verification Methodology, or OVM, is an attempt to bundle SystemVerilog interoperability with a standard library and a proven verification methodology.
Exploding complexity is an overarching challenge of IC design. The industry’s response: a reliance on standard protocols such as PCI express, USB and reusable blocks of intellectual property (IP). These functional elements have allowed innovation to continue.
However, even as designers have become adept in assembling discrete, functional IP for popular end-user systems, new problems still emerged: How can you efficiently scale large, complex designs? And how can you do so while creating reusable verification testbenches that are sufficient for future design projects?
Open Verification Methodology, or OVM, was created to address these increasingly expensive issues. Available for download under the Apache 2.0 licence, OVM is an attempt to bundle SystemVerilog interoperability with a standard library and a proven verification methodology. The joint Cadence-Mentor Graphics creation is usable on most of the world's SystemVerilog simulators and is a platform for development of reusable verification IP.
OVM represents a complete embrace of standards and openness. SystemVerilog, the IEEE hardware description language, forms the foundation of OVM. And OVM’s core transaction level modeling (TLM) functionality is based on the OSCI TLM standard, itself soon to become an IEEE standard. Developed and backed by two major EDA companies and supported by a vibrant user community through the OVM Advisory Group (OAG), OVM is arguably already a de facto standard.
To understand OVM’s significance, consider a brief history of the EDA industry. Not long ago, EDA tool vendors would each invent their own languages and file formats. This was fine until transistor geometries started to significantly shrink. The expanded silicon real estate afforded by smaller process technologies provided opportunities to build new electronic devices, from cell phones to medical tools. However the proliferation of available transistors also made it impossible for a single design team to produce a marketable chip, a situation that prompted the well-known rise of reusable IP.
Perhaps less understood is the connection between reusable IP and standards. Faced with hooking together a dizzying array of IP blocks, designers looked to standard protocols such as PCI Express and USB. Engineers also demanded their tool vendors provide standard languages and data exchange formats. Standards were incorporated into more of the design process, allowing design teams to encapsulate functionality and make it available through well defined interfaces.
As a result, innovation mostly flourished as IC designers were able to work within the confines of these well defined interfaces and ignore other aspects of the system.
I say “mostly” because all these blocks and systems need to be verified. Building a testbench for a block has always been an interesting challenge all by itself. But now the essential problem is not just building a testbench, but building a reusable testbench – one that can be used by the subsystem integrator and again the system integrator.
OVM releases some of this tension and encourages continued cost-effective innovation. It’s fundamentally about freeing design teams from the encumbrances of too many low-level details. Of course, the benefits of standards can be seen far beyond IC design. Consider the plight of a building architect who had to invent nails, plywood, paint, and so forth for each new building. Very few buildings would be built and skylines would likely be very primitive.
Or closer to home, where would the software industry be without standard languages such as C++, Java and Perl? Programmers can now think about object composition instead of code for string manipulation, for example.
Because these languages are themselves standards, either de jure or de facto, low-level problems remain solved for a long time, thus future-proofing the solution to higher-level coding problems. OVM’s embrace of openness takes a page from the software development community, which has arguably been transformed by open source.
Designs have scaled from thousands to millions to now over a billion gates on a single die and verification methodologies have not similarly scaled. Until now. OVM provides a highly scalable verification methodology that enables innovation in testbench construction as well as support for the manufacture of innovative designs.
Author is Mark Glasser, a methodology architect and the author of the “Open Verification Methodology Cookbook”.
Contact him at mark_glasser@mentor.com