The EU is funding a European consortium to improve sub-wavelength lithography and associated EDA tools.
The aim is to find a way past the current choice at 32nm and below between computationally intensive layout tools that achieve high gate density, and restricted tools that cost less to use but generate looser layouts.
"Through use of a more restrictive set of layout patterns with predictable layout neighbourhood, variability caused by the physical limitations of current industrial lithography techniques can be reduced and manufacturing yield can be improved," said the consortium.
"An additional benefit of this approach is that it eases RET [resolution enhancement technology] computation and hence reduces mask generation complexity."
"However, in particular for implementation of random logic with state-of-the-art automated implementation methodologies, the layout restrictions lead to loss of density of the logic cell libraries and a reduced block-level gate density when compared with traditional methodology utilising cell libraries with more complex layout patterns. "
For this reason, complex patterned logic cells followed by advanced mask processing steps have continued to be the dominating approach.
At 32nm and below, significant layout restrictions lead to a more regular layout style being applied for fundamental logic cells. However, it is necessary to counter the negative effects of regularity restrictions on logic density.
"It is therefore critically important to focus research efforts on exploring and developing innovative design techniques and methodologies, along with associated CAD tools and logic cell libraries, which remove the limitations in design implementation effectiveness associated with technology scaling and advanced sub-wavelength lithography," said Denmark-based Nangate which is coordinating the project, now dubbed Synaptic.
Synaptic aims to develop a revised design methodology in which the concept of regularity is propagated through all abstraction levels: architectural, logic and physical layout.
"From an architectural point of view, the advantages of the proposed methodology include the ability to exploit step and repeat approaches employing complex logic cells and complex logic building blocks, thus providing greater predictability of design performance and enabling comprehensive early architecture exploration," said Nangate.
"Reliance upon complex logic cells and logic building blocks realised by regular layout patterns reduces sensitivity to process variations, improves performance predictability and enables tighter design margins."
From a logic design point of view, it is claimed, the advantages include the creation of logic cell libraries targeted to design requirements, thus improving performance and performance predictability.
From a physical design point of view, said Nangate, this approach will enable the use of lower-cost lithography techniques as compared to complex patterned logic cell approaches while achieving the same yield.
With Nangate, the consortium partners are: chip maker STMicroelectronics; aerospace and defence giant Thales (France), semiconductor lab IMEC (Belgium), the university Politecnico di Milano (Italy), Universitat Politecnica de Catalunya (Spain), Universidade Federal do Rio Grande do Sul (Brazil), and EDA consultancy Leading Edge.
Funding is being delivered through the Seventh Framework Programme.