There are ways of making power reduction in your chip design more predicatable and they usually involve good power analysis, writes Pete Hardee.
What are the good techniques for low-power design? Designers have used basic techniques like clock gating and multiple threshold voltage (MVt) library cells for many years.
Both techniques are now fairly well automated in synthesis and implementation tools. As we adopted new process nodes and leakage increased, further techniques emerged involving separately supplied power domains. These techniques include:
• Multiple supply voltages (MSV) – this technique uses different levels of Vdd to permanently supply various domains as the balance of performance versus power dictates. MSV can reduce dynamic and leakage power, but needs level shifters on signals crossing the domains.
• Power shutoff – this technique is also known as power gating, or state retention power gating (SRPG). It reduces leakage by completely powering-off idle circuitry. State retention registers speed the return to full operation on power-up. Complications include implementing the power switch network and ensuring that isolation cells fully prevent the propagation of unknown states from off-domains to on-domains.
• Dynamic voltage and frequency scaling (DVFS) – this technique changes both the voltage level and clock frequency dynamically, based on current performance demand. DVFS works well on blocks whose performance demand can be relatively easily measured, such as processor cores.
However, the number of voltage and frequency levels exponentially increases the number of modes and corners at which design closure needs to be validated. There are obvious complications when implementing level shifters and dynamically changing power supplies.
These techniques cause design and verification complexity, which increases greatly with the number of power modes. This is, in turn, a function of the number of domains and the number of states those domains can occupy.
These power domain–based techniques led to the need for new power intent formats to specify them, including the Unified Power Format (UPF – now IEEE-1801) and the Common Power Format (CPF – standardised by Si2).
Low-power design techniques are architectural in nature, hence the power architecture has to be decided early in the design cycle - it is nigh impossible to retro-fit. This leads to an obvious question: how do I know that the techniques I choose will enable me to meet the power specification?
The answer is early power analysis. What is needed for good power analysis?
Fundamentally, power boils down to be a function of two things: characterisation and switching activity. Characterisation means accurately modelling what happens when a transistor switches - it’s a function of Vdd2, R, and C.
Switching activity means the frequency and duty cycle for each of the transistors in the circuit of interest. Characterisation has dominated thinking to date in power analysis, leading to the idea that there is acceptable accuracy only when there is a placed-and-routed netlist and all of the transistors and wires are known, and all of the RC values are extracted.
However, characterisation no longer seems to be the problem designers are struggling with; rather, it’s the activity. What system modes are needed to generate realistic activity in today’s multi-function devices? Am I replicating those with my vectors or am I just running test patterns that bear scant relation to real-life operation of the device? Do I need to look at average activity over a long time to gauge energy and thus battery life? Or do I need to look at peaks in activity, which will point to thermal problems?
The so-called accurate power analysis tools operating at the gate level or the physical netlist level may not be at all representative if it is not possible to use representative activity vectors.
On the other hand, it may be easier to analyse real activity driven by executing system software, but accurate characterisation is missing.
One approach is called dynamic power analysis. Using hardware emulation technology designers can run as much real system-level activity as necessary, and they can run real system modes under software control. The resultant activity is measured on all relevant points in the design mapped onto the emulator.
This is exactly what the emulator is designed to do. And as the hardware design is being mapped to the emulator, in parallel the design is characterised using logic synthesis technology to map the design to the real cell library.
Author Pete Hardee is a marketing director at Cadence Design Systems