Guest columnist Shawn McCloud, product line director for the Mentor Graphics high-level synthesis technology, says the latest generation of high level synthesis technology overcomes the limitations of the first release of tools.
For high level synthesis (HLS) tools to scale and keep pace with designs of the future, they must be able to handle large, complex designs in their entirety.
To do this, they must be able to design and assemble blocks of different abstractions and input languages—from legacy RTL to cycle accurate SystemC to untimed algorithmic C code. They must be able to do this with an intuitive and predictable methodology so that productivity scales with design size and complexity.
Such tools will carry EDA to the next step in its evolution, enabling more complex, larger, nanotechnology designs to be produced quickly and competitively.
Only a few of the dozen or so HLS tools offered today have the level of maturity and robustness to support the move from a top-down to a modular HLS design flow. Initially, HLS took a block level approach, following the tradition of hardware architects to partition designs according to what individual hardware designers could handle.
First release HLS tools did not have the capacity to handle all aspects of an SoC; thus, some parts were done in C while others remained in hand-coded RTL. However, the latest generation of HLS technology overcomes these limitations by enabling modular design and assembly.
An HLS modular strategy divides complex systems into heterogeneous hierarchical blocks and provides legal interface synthesis for designers to plug and play these different abstractions together.
In other words, these tools have the ability to mix legacy RTL with multi-abstraction, C-level blocks, enabling the representation of all design functionality at the system level of abstraction without converting legacy RTL code to C.
This increases productivity, reduces risk, and yields greater flexibility while helping design teams manage design complexity, leverage legacy RTL, and increase capacity. Just as we saw with RTL reuse, we will see the creation and reuse of C++ IP and the ability to incorporate that into increasingly larger, more complex designs.
This HLS modular approach is a big step forward for designers for three key reasons:
- Teams can divide-and-conquer designs.
- Designers can follow a build-as-you-go process.
- Physical effects can be locked down and linked back to C-level models.
HLS tools that provide design partitioning support team design, and increasing the capacity to design by spreading the design across teams. This ability to divide-and-conquer allows design teams to break up very complicated, large, hardware sub-systems into manageable pieces that individual designers in a team can work on independently.
For this approach to be successful, these HLS tools must include features that provide predictability as to how those pieces will be verified individually, integrated into the larger sub-system, and then verified together as the larger SoC.
The modular HLS approach must support incremental design. As design blocks are assembled into very large subsystems, designers can preserve their optimised blocks throughout the design flow.
The ability to build-as-you-go allows design teams to freeze the majority of their hardware subsystem and re-optimise only those blocks required to implement a design change. In other words, it allows designers to isolate those changes to a sub-block and keep the rest of the system untouched.
In a modular HLS flow each untimed block can be designed in isolation and fully optimised, then instantiated in another design where it is referenced but not synthesised. Top-level synthesis becomes a matter of creating the interconnect.
Incremental design also allows HLS to scale to 100 million gate SoCs and, theoretically, beyond, because it builds blocks of reusable C++ IP that are highly configurable, highly parameterised, and hardware neutral.
As design teams move to next-generation SoCs, they will be able to leverage these legacy blocks and sub-systems and incorporate them into larger systems, then optimise them for specific area, performance, and power goals. This will be an important step forward similar to what we have seen in today’s RTL SoCs, where tremendous RTL design reuse enabled the creation of 20 million gate SoCs.
The ability to lock down physical effects and link them to C-level models allows the annotation of correct, accurate implementation details. This will be particularly necessary as we move into the 0.32µm geometries and lower, and as we begin to see very high frequencies in the 1 to 2GHz range.
To support a modular approach, an HLS tool must be able to associate new hardware blocks with the physical effects—all the way to place-and-route—and annotate that information back to the design being synthesised in C. These advanced HLS tools will make adjustments to the C-level designs to satisfy the physical effects and fix any violations that may have occurred. Once that iteration has occurred, the implementation-accurate estimates for blocks that are fundamentally critical can be locked down.
Modular HLS design and assembly capabilities will enable HLS tools to handle highly complex, massive designs in their entirety. With this powerful capability, HLS will broaden its reach and acceptance for the production of the largest and most complex systems attainable. In fact, it is what will make these types of systems possible at all.
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