Low voltage CMOS technology firm SuVolta has licensed Magma Design Automation's FineSim SPICE circuit simulator.
SuVolta's intellectual property, called deeply depleted channel (DDC), allows the distribution of transistor threshold voltages across a chip to be tightened significantly, without moving away from standard bulk-silicon techniques.
Fujitsu used DDC transistors to cut the operation voltage of SRAM blocks from 1.2V to 0.9V, (840µW to 170µW consumption).
"Using FineSim SPICE, SuVolta reduced simulation runtime, enabling the design team to increase test coverage by 4x without sacrificing accuracy," clamed Magma.
FineSim incorporates transistor-level simulation analysis capabilities for mixed-signal and analogue designs.
It can be run on distributed processing, allowing large-scale mixed-signal chips to be simulated.