Taiwan Semiconductor Manufacturing Company says it has developed a 28nm low power process technology that continues the scaling trend and extends Silicon Oxynitride (SiON)/poly usage beyond 32nm with a dual/triple gate oxide process.
The significance of this is that it could demonstrate SiON/Poly technology as being commercially feasible as a low power SRAM process.
TSMC's paper described transistors using SiON optimized with strain engineering and aggressive oxide thickness which provides 25-40% speed improvement or 30-50% active power reduction over prior 45nm technology.
“This development was achieved through close collaboration with customers who are pushing their own boundaries of new applications requiring 28nm technology,” said Dr. Jack Sun, vice president R&D at TSMC.
Other characteristics from this technology includes high density and low Vcc (min) 6-T SRAM cells, low leakage transistors, well-proven conventional analogue/RF/electrical fuse components and low-RC Cu-low-k interconnect.
This development was presented this week at the 2009 Symposia on VLSI Technology and Circuits in Kyoto, Japan.
TSMC reported good 64Mbit SRAM functional yield with a competitive cell size of 0.127 um², and a raw gate density as high as 3900 kGate/mm² in this 28nm dual/triple gate oxide SoC technology.
TSMC has said it plans to deliver its 28nm process in early 2010 as a full node technology offering options of power-efficient high performance and lower power technologies.
See: Foundry industry on a roll