Soitec, the silicon-on-insulator (SOI) wafer specialist, has announced a 300mm SOI wafer platform qualified to support fully depleted (FD) device applications on 22nm CMOS processes.
The 300mm UTSOI wafer platform is fabricated using the company's patented Smart Cut technology.
France-based Soitec said it can manufacture SOI with extremely thin top-layer silicon (20nm) to a thickness uniformity tolerance of +/-0.5nm in high volume with high yields.
This could open the way for fully depleted SOI process technology to be used to fab devices for mainstream applications.
"On fully depleted SOI, we've demonstrated 25nm high-k metal-gate devices with matching characteristics far superior to those obtained on bulk silicon," reported Dr. Olivier Faynot, director of advanced SOI technologies development at CEA-Leti.
"As it eliminates the need to dope the channel region, FD SOI solves threshold voltage (Vt) variability challenges at current and future nodes, while maintaining excellent Ion and Ioff characteristics and drastically reducing gate leakage current," said Faynot.
The company claimed its ultra-thin SOI technology will allow designers to cut power consumption and leakage while preserving performance.
"It simplifies the overall CMOS architecture, thus reducing the cost of ownership below a bulk approach," stated Paul Boudre, Chief Operating Officer of the Soitec Group.