Automated compiler technology for custom processor designersRichard Ball in MunichAt the DATE design automation conference last week, two firms were showing off automated compiler creation tools for processor designers. Target allows custom processors to be designed with a compiler created automatically.
Target Compiler Technologies has a tool called Chess which takes a simple model of a processor
and automatically produces a re-targetable compiler, assembler, linker and an instruction set simulator (ISS) for that architecture.
"The designer doesn't need to know how Chess works to write rules," said Tony Picard, sales and marketing manager at Target. And the processor model is easy to write, he claimed.
Real application code can then be written and run on the ISS. If the performance is not right, the processor itself can be altered, perhaps
adding or removing execution units. This iterative process refines the processor design very early in the project.
One of the first firms to use this technology is Philips. "CoolFlow is an ultra-low power DSP application designed by Philips," said Picard. It is an eight-way processor aimed at hearing aid type applications.
Using the Chess tool, "has allowed us to gain a lot of productivity", said Patrick Vendebroek, from Philips' digital systems laboratories.
The complete DSP was created in less than one year by two designers, he said.
A similar technique is being used by CoWare, through its recent acquisition of German firm LisaTek.
CoWare was among the first companies to produce system level design tools, and helped define SystemC.
The LisaTek tools also use a proprietary language, Lisa - language for instruction set architectures - to define a processor, and from this creates an ISS and software tool chain.
Moreover, the CoWare link takes the description of the processor into N2C, its hardware/software co-design tool.
Target has a similar facility through a tool called Go, which takes the processor model and produces synthesisable VHDL for an FPGA or Asic.