EDA start-up CriticalBlue said it has completed a project that
saw its embedded processor development tools integrated with
Synopsys' hardware development flow.
CriticalBlue's Cascade tool was used to explore the architecture
of the system and produce synthesisable RTL for a co-processor.
Design Compiler and VCS from Synopsys were used take the logical
design to gates.
"Synopsys has a long history of supporting emerging EDA
companies who provide complementary parts of the design flow. Our
customers expect us to enable a degree of validation of these new
tools with respect to our trusted flows and we are happy to support
this activity," said Karen Bartleson, director of interoperability
at Synopsys.
The project, for an unnamed firm, was for an error correction
circuit used in wireless comms. Source code, aimed at an ARM
processor, was profiled by Cascade which produced a choice of
architectures.
Designers could trade-off gate count and performance before
choosing the most suitable co-processor to run parts of the code.
The resulting system is aimed at 0.13µm technology.
Cascade not only produces the architecture and co-processor RTL,
but also microcode and the testbench for verification.
"The purpose of validating the flow through the Synopsys RTL
implementation flow was to verify the interoperability of the RTL
code that Cascade generates and ensure the gate count and
performance goal are met," said David Stewart, CEO of
CriticalBlue.
www.criticalblue.com