French start-up Arteris has unveiled its tools that implement network-on-chip technology to replace conventional bus structures.

Test chips made at 90nm show serial links can transfer data at up to 6Gbyte/s, while saving die area compared to wide busses.

"This is silicon proven - it's not just a research idea," said Alain Fanet, president of Arteris.

The firm has taken networking concepts and applied them on-chip. Blocks of IP, processors and memory all gain a physical interface, analogous to a PHY, and called a network interface unit.

Meanwhile on-chip switches are used to route data. Each crossbar switch can be up to 8x8 in size. To link more blocks of IP, switches can be linked with either synchronous or asynchronous data links.

On top of this physical layer sits a packet transport layer, while to interface with existing IP a transaction layer makes the network look like a standard bus.

"We apply some quality of service technology to guarantee packets are not dropped," said Fanet.

The first tools allow designers to create the network topology and then produce the required RTL, scripts and associated data for linking with the rest of the design.

Fanet said the IP and tools the firm is offering is comparable in value to the microprocessors developed by ARM or the external bus structures from Rambus. A single design licence for the technology will cost between $350,000 and $500,000.

www.arteris.net