Bluetooth was the proving ground for implementing multi-gigahertz RF transceiver circuits on a cost-effective CMOS process. The success of CMOS RF advocate CSR from Cambridge is testament to that.

Yet silicon suppliers have not stopped there. The big prize for CMOS RF designs will be the next generation of cost and size sensitive 3G mobile phones.

Silicon Laboratories is one supplier which has been shipping a GSM/GPRS mobile phone transceiver for two years and last year it complemented this with a highly integrated power amplifier (PA). But the mobile market is not standing still and now suppliers are looking at how to use the cost benefits of CMOS RF circuits in next generation phones.

“3G designs are achievable in CMOS - no one should be scared about doing wideband CDMA RF designs in CMOS,” says Dan Rabinvoitsj, v-p of wireless products at Silicon Labs.

Despite Rabinvoitsj’s confidence, these are relatively early days for using CMOS front ends in mobile phones. Take the back off many GSM handsets and it will be a gallium arsenide (GaAs), not silicon, RF front end and PA which you find, probably supplied by RF Micro Devices. But that is the target market for silicon RF specialists such as Silicon Labs, Texas Instruments, Renesas Technology and National Semiconductor.

It is the adoption of digital radio technologies such as GSM and CDMA which makes all CMOS RF mobile phone transceivers possible at all. Whereas implementation of classical radio architectures pose an almost insurmountable challenge in deep submicron CMOS, sampled-data radio architectures make possible the use of CMOS and the ability to scale with process.

The real cost benefits of all CMOS RF devices will only be realised if the chips can be fabbed on as near as possible a standard CMOS process in the foundry or ODM. But the inherent scaling of CMOS processes, driven by mainstream digital products, poses its own problems for RF circuits.

Texas Instruments (TI) believes that scaling of CMOS to lower and lower voltage levels makes analogue design more difficult as process technology advances. Device modelling and process maturity early in the development of a new process node are generally inadequate for highly accurate parametric modelling required for these analogue type block designs.

What does the industry mean by CMOS RF? The phrase covers a range of products fabbed on different process technologies. It ranges from the all-CMOS ICs of Silicon Labs - produced in a standard CMOS process with a couple of changes to the insulation layers to support on-chip capacitors and inductors - through to BiCMOS, bipolar hybrid technology, and silicon germanium.

According to TI, CMOS mobile phone radio designs have build heavily on analogue functions. Implementation of the analogue mixers, filters, and amplifiers in CMOS technology is difficult and the power consumption can be higher than for an alternative SiGe BiCMOS design.

While SiGe BiCMOS will easily achieve all the performance requirements needed for mobile phone front ends it does not offer the cost benefits of a ‘pure’ CMOS RF design. According to Mark Norris, RF specialist at Cambridge Consultants, integrating a SiGe process can add as much as 30 per cent to the mask costs.

Whereas all-CMOS designs can make use of the economies of scale of using ‘standard’ CMOS foundries with a few tweaks in the process such as a thick metal layer for high Q inductors, an insulation layer for metal-insulator-metal (MIM) capacitors and perhaps a high resistivity polysilicon layer. “But these are not as involved as integrating SiGe,” says Norris.

Rabinvoitsj at Silicon Labs argues that their approach is even simpler: “We do not believe you need a high resistivity substrate.”

Renesas Technology, another big RF chipset supplier, uses a BiCMOS process which it has perfected to be more cost-effective. “The all-CMOS approach is to take a CMOS process and make it more complex by adding high Q inductors and capacitors. We take a BiCMOS process and simplify it,” says Stephen Graham, RF marketing manager at Renesas.

Renesas’ approach is to use an NPN transistor only BiCMOS process. “This means in practice there is only a couple of mask steps difference to CMOS,” says Graham.

Cost is the big driver for moving next generation mobile phone RF designs to CMOS. But will the cost benefits of using a commercial 90nm or even 65nm CMOS process be nullified by design constraints at smaller geometries?

According to Rabinvoitsj, the problems which analogue design faced in the move to 90nm process have been addressed with the move to 65nm. “90nm may not be ideal for analogue/mixed signal but the situation has improved with 65nm,” says Rabinvoitsj. “Foundries have addressed our requirements.”

What will be the impact on analogue circuit design as working voltages drop to 1V for a 65nm process? “This must impact circuit topologies, the lack of headroom for transistors,” says Norris.

But according to Rabinvoitsj: “The voltage drop is manageable.”

Graham from Renesas argues that process cost savings with CMOS can be offset by the smaller die size of BiCMOS designs.

The other cost driver is the potential of greater system integration. But realistically this is still some way off for 3G and even GSM handsets. While integrated CMOS RF and baseband designs have been achieved for lower power Bluetooth there may yet be fundamental obstacles in the way for 3G handsets. “Small signal electronics must operate under [crosstalk] blocks and those blockers are on the same chip. That is a tough problem,” adds Rabinvoitsj.

www.cambridgeconsultants.com
www.renesas.com
www.silabs.com
www.ti.com