Georgia Tech has developed a CMOS-compatible way to add fluid cooling channels to chips.

“By integrating the cooling microchannels directly into the chip, we can eliminate a lot of the thermal interface issues that are of great concern,” said research assistant Bing Dang.

“This scheme offers a simple and compact solution to transfer cooling liquid directly into a gigascale integrated chip. It is fully compatible with conventional flip-chip packaging.”

The wafer-level fabrication technique includes polymer pipes which Georgia claims will allow electronic and cooling connections to be made simultaneously during automated flip-chip PCB assembly.

Bing Dang from Georgia Tech

The team starts by etching trenches “more than 100µm deep” in the back of the silicon wafer.

A layer of high-viscosity sacrificial polymer is then spin-coated over the back of the chips, filling in the trenches. Excess polymer is polished off.

The filled trenches are then covered by a porous overcoat, and polymer decomposed by heating in a nitrogen atmosphere, which leaves covered channels.

A second polymer layer deposited over the porous overcoat waterproofs it and completes the coolant-tight channels.

Vias right through the thickness of the wafer allow fluid into the channels, and these are connected to the PCB trough specially-developed flip-chip-compatible polymer connection pipes.

Simultaneous fluid and electrical connection has been demonstrated, claims the team, resulting in a working coolant system that has so-far been tested for several hours using buffered de-ionised water to remove heat.

The channels can cope with over 35psi pressure and both on-board and centralised pumps are proposed. The technique can also be used on multi-chip stacks.

“Calculations show that the system, which can have either straight-line or serpentine microchannel configurations, should be able to cool 100W/cm²,” said Georgia.

“Heat removal capacity depends on the flow rate of the coolant and its pressure, with smaller diameter microchannels more efficient at heat transfer,” it said.

The Georgia Tech approach is CMOS-compatible, needing less than 260°C during processing.

Other microchannel covering techniques use wafer-bonding, said Georgia, which needs processing at between 400 and 700°C, eroding or exceeding transistor thermal budgets.

Additional testing is needed to confirm long-term reliability, said Dang.