Time-to-market drives SoC design to higher levels of
abstraction as firms look to differentiate, saysRalph von
Vignau from Philips Semiconductors
Achieving short time-to-market is a major driving force in
today’s semiconductor industry. For the consumer electronics
industry it represents the single most effective way of maximising
semiconductor sales and profit. In terms of its financial
implications, it is already more important than hand-crafting the
last few hundred square microns of silicon area out of a
system-on-chip (SoC) design.
Acceleration of the ITRS (International Technology Roadmap for
Semiconductors) has resulted in the early introduction of 90nm CMOS
manufacturing and an expected smooth migration to 65nm CMOS. As a
result, semiconductor manufacturers can realistically expect to
leverage the cost advantages of these new technology nodes within
the lifetime of existing product designs in order to maintain
competitive price curves.
At the same time, however, these new technology nodes are
allowing the design of far more complex chips. Reducing
time-to-market for these complex SoCs therefore depends on managing
an ever-increasing level of complexity in a way that cuts both
design and verification times.
Achieving these objectives will require aggressive changes in
the way SoC designs are driven within the industry, together with
partnerships between companies to drive forward standards for
inter-operability of IP (intellectual property) in all its shapes
and forms. Such standards are already being promoted for
industry-wide use by organisations such as the SPIRIT (Structure
for Packaging, Integrating and Re-using IP within Tool-flows)
consortium.
However, it is also essential that this IP is made available to
chip designers in a way that allows them to easily select it,
understand its capabilities and import it into their SoC design
environment.
To achieve this capability for its internal SoC design teams and
external development partners, which represent a microcosm of an
industry that increasingly needs to share IP, Philips
Semiconductors has developed a web-based application that it calls
‘IP Yellow Pages’. Accessed via a secure web-server, the IP Yellow
Pages website allows designers to browse IP libraries or to locate
suitable IP with the aid of a search engine.
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Philip's IP library system - its 'Yellow
Pages' |
For each library entry, an IP Profile web page provides an
overview of the IP’s attributes, documentation, deliverables,
development status and level of support. It also details any
associated usage, maintenance and royalty fees.
Chip designers can then download the IP required from the server
via a web-based or command-line interface.
The website includes both hardware and software IP and will soon
allow the ordering and order-tracking of use-specific memory
configurations. The site also acts as a shop window for the
promotion of new IP that is added to the library.
Although such systems make IP readily accessible in a usable
form and thereby eliminate much of the ‘re-invention of the wheel’
that still goes on in the chip industry, they must be supported by
a design environment in which that IP can be speedily assembled
into a SoC.
To manage the competing requirements of increasing complexity
and shorter time-to-market, this design environment must be capable
of taking SoC design to the next level of abstraction by allowing
the rapid generation, configuration and verification of re-usable
sub-systems. In order to do so it must be able to address system
architecture considerations as well as IP block assembly, steering
designers towards sub-system and SoC architectures that are suited
both to the application and to the available IP.
To cope with the increasing use of IP from third-party IP
vendors and joint-ventures, such design systems should be based on
industry standards for IP re-use and commercially supported EDA
tools.
These underlying principles are illustrated by Philips’
Nx-Builder design environment. This is built around Mentor
Graphics’ Platform Express XML-based SoC design creation tools,
Synopsys’ coreAssembler sub-system assembly and configuration tools
and Prosilog’s GUI-based Magillem SoC design tools, all of which
support the SPIRIT specifications.
It uses Philips’ SPIRIT-compliant IP Yellow Pages as its IP
portfolio. These components combine to create an environment in
which SoC design becomes almost a drag-and-drop exercise.
The benefits of such a system are considerable.
Design and verification cycles are significantly reduced, with
functions such as interconnect verification, infrastructure
verification and IP interoperability being almost fully automated.
Chip composition and parameter derivation for reconfigurable IP is
improved, and the system provides a single source for system
documentation.
By facilitating the generation of reproducible chip designs that
are far less dependent on a single design engineer, such systems
reduce design risk and encourage future IP re-use. Time-to-market
reduction can be as much as 25 per cent for new SoC designs, and 75
per cent for straightforward derivatives.
By simplifying and automating SoC design by an order of
magnitude compared to previous methods, these environments pave the
way for the next shift in the industry – the move to ESL
(electronic system level).
Targeted at high-level hardware/software co-design using
SystemC, ESL will allow designers to make critical
hardware/software trade-offs very early on in the design cycle,
further minimising design risk.
By using the same programming language for both hardware and
software development, it will be possible to simulate and verify
the entire application before having to lock any of the hardware
design into silicon.
In conjunction with compiler development environments that can
automatically generate compilers from SystemC descriptions, it will
even allow software instruction sets to be customised to suit
specific architectures and application requirements.
In a business environment where semiconductor companies have to
provide comprehensive software stacks with their SoCs simply to
sell silicon, the ability to minimise risk and shorten
time-to-market through hardware/software co-design will be a new
enabler for differentiation.
The richness of their IP libraries and the applicability of the
platform architectures into which they can integrate this IP will
only be part of the story. It will be their ability to partition
the hardware and software in SoCs to combine cost-effective silicon
with high-performance software stacks, and their ability to deliver
the total package on-time to the customer that will differentiate
them in the market place.
Ralph von Vignau is director infrastructure & standards
of the Chief Technology Office at Philips Semiconductors