Renesas Technology has revealed more details of its capacitor-less, twin-transistor RAM that can be built in a standard silicon-on-insulator (SOI) CMOS process and reduces power and cell size compared to DRAM. It is intended for embedded memories at the 65nm process generation and beyond.

Without using features such as DDR, a 130nm 2Mbit test chip operated at 250MHz in continuous data output mode and 133MHz in random access mode. Active power consumption was 148mW, and the memory cell occupied 0.33µm².

Fukashi Morishita, an engineer in the system core technology division at Renesas, said the TTRAM could be implemented successfully thanks to both the low supply voltages used in a modern 130nm SOI-CMOS process, and the ability to realise a floating-body SOI transistor in those processes.

“In previous process technology excessive current flow there was during the read operation,” said Morishita. “Supply voltage lowering enables the coexistence of TTRAM operation and high-speed logic operation.”

In the TTRAM cell two transistors are serially connected, with one operating as an access transistor, and the other as a storage transistor. The latter performs the same role as the capacitor in a conventional DRAM cell. Data is read and written according to the conduction state of the access transistor and the floating-body potential state of the storage transistor.

The company said the TTRAM structure has advantages over one-transistor gain cells, including low-voltage operation, simple control, and no requirement for extra process steps. Although the test chip was limited by silicon area to 2Mbit (2mm²), in production 512Mbit cells would be possible.

“Another benefit is from the viewpoint of power-efficiency,” continued Morishita. “SOI devices themselves reduce power because of lower parasitic capacitance. In addition, the TTRAM-cell doesn’t require a boosted voltage or negative voltage, which is required for DRAM. As a result, the active power is 43 per cent less than DRAM in the same conditions.”

Renesas says at the moment the biggest drawback to the technology is the need to use a comparatively expensive SOI-CMOS process. However, it expects the cost of SOI to fall as its use becomes more common.

www.renesas.com