Looking forward to sub-45nm chips, one of IMEC’s research programmes is in interconnection, particularly the problems of low-k dielectrics.

Needed to reduce capacitance between metal layers and the chip surface, low-k dielectrics are essentially ridged silicon-oxygen-carbon foams whose holey nature makes them physically weak and porous.

Rudy Cartuyvels is director of interconnection technology at IMEC. He has been studying low-k dielectrics proposed for sub-45nm devices. “Intrinsic properties are definitely improving,” he said.

In recent tests, four latest-generation materials - un-named for commercial reasons - were tested and all had pores below 2nm, with porosities ranging from 14 to 30 per cent. K-values were between 2.5 and 2.7, compared with 3.9 for SiO₂.

Young’s modulus, a measure of how much the materials deform permanently under force, is between six and nine gigapascals, something that can be improved by some 40 per cent by un-specified UV-assisted curing with little increase in k. Using alternative curing, figures of 16GPa at k=3.2, and a jump from 2 to 4GPa at k=2.1 have been reported.

Before metal is deposited over low-k dielectrics, the vertical and horizontal surfaces of the material have to be sealed to prevent metal entering its pores.

Surface densification - essentially smearing the material’s surface to seal it - looks like it will run out of steam above 22 per cent porosity said IMEC, limiting its use to materials of k>2.4. Below this, additive surface coating, by plasma deposition or wet chemistry, appears essential.

Both the sidewalls and top of low-k dielectrics are damaged during plasma patterning with as much as 25nm of k=3.0 materials stripped of carbon and converted to k-increasing SiO2, said Cartuyvels. Most of this damage occurs on top, where it can be reduced by depositing a sacrificial metallic hard mask. IMEC’s best hard mask-protected results show less than 5nm damage.

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