Simplifying debug in FPGAs is the trigger for a three way alliance involving Altera, Tektronix and First Silicon Solutions (FS2).

The design co-operation for real-time debugging of Altera FPGAs is based on the FPGAView software package from FS2 running on a Tektronix TLA logic analyser. The software measures signals inside the FPGA and then allows the designer to select which internal signals can be probed without having to recompile their design.

“With the ever increasing density of FPGAs, designers are looking for more productive means of debugging internal nodes of the device,” said David Bennett, v-p for the logic analyser product line at Tektronix.

Once installed on an analyser, the debug software is enabled by an interface feature introduced in Altera’s Quartus II design software version 5.1.

With the analyser connected to the FPGA through a JTAG port, the software controls which internal FPGA signals are mapped to the output pins for real-time display and debug.

www.altera.com
www.fs2.com
www.tektronix.com