Programmable logic is becoming more fixed function, and hard-wired logic is becoming more programmable. The programmables add more and more fixed functionality, while hardwired Asics and SoCs add more programmable gates to broaden their applications.

Meanwhile, both logic types face common problems: the power problem of leakage in sub-100nm chips which is putting a ceiling on performance; and the time and cost problem involved in the design and verification of Asics and SoCs, which makes designers look for EDA tools which can design at the system level.

The ideal chip is programmable, low power, containing the best fixed IP, works first time at the fab, retains the silicon efficiency of custom chips and is programmable at the algorithmic level in C. This is a pipedream. But many people are trying to resolve parts of the dream.

Graham Curren

“People won’t design 65nm designs from scratch; they won’t put down 100 million transistors. Chips will be on-going devices which evolve over time,” suggests Graham Curren, CEO of Sondrel. This is the platform approach.

“It will cost $50m to develop a 65nm chip,” says Ronnie Vasishta, CEO of eAsic. “The problem is how to move to a new level of abstraction. We need an era of more designs per engineer, and not more engineers per design.”

“The lesson of history is to abstract up beyond the level of the problem. We’re moving into algorithms, and abstracting them above the silicon,” says Kenn Lamb, CEO of Elixent.

But it is not easy. “You can’t abstract away from the silicon and still get optimal performance,” says Celoxica’s CEO, Phil Bishop, whose company’s C-programmable system-level technology can reduce design time by between 40 and 50 per cent, but results in a 25 per cent reduction in chip performance.

Wolfgang Rosenstiel of the University of Tubingen, says that the MEDEA+ SpEAC project, aimed at moving design to a higher level of abstraction, has resulted in a 75 per cent reduction in design time and 80 per cent reduction in verification time, reducing the time from design to fab from between nine to twelve months, to between seven to ten months.

While efforts persist to move design to a higher plane, the costs and time involved in creating a chip just keep growing.

“From idea to first chip sold, is at least three years, and most of that time is taken up by testing and qualifying,” says Rudi de Winter, CEO of Melexis.

Phil Bishop

Some estimate the cost of verification at 70 per cent of the total cost of a chip’s development. To cope with the problem, the concept of setting up ‘design foundries’ in low-cost areas to perform routine design work is being discussed.

Some have found ways to short-circuit the SoC design process. “The customer defines the architecture, the chip size, the I/O cells. We fill up the remaining area with gate array cells and pre-produce this while the customer is still producing the logic,” says Toshiba’s Rainer Kase.

“Once he’s completed verifying the logic, we’ve already made the base wafer, and can draw the customer’s logic on it using e-beam.” In this way Toshiba can produce a 90nm SoC in under a year for between $3m and $5m.

Structured Asics which customise just two or three layers of a chip, are another way to reduce production costs.

Other efforts have sought to add greater flexibility and therefore wider applicability to SoCs which would allow the rising costs to be amortised over a wider user base.

Efforts by companies like Spiral Gateway, eAsic, M2000 and the ill-fated STMicroelectronics’ GOSPL project, look at providing C-programmable, re-configurable, low power embedded FPGA for SoCs.

This is proving to be a big challenge as STMicroelectronics demonstrated when it pulled the plug on GOSPL after spending an estimated $50m on the project.

The problem is that FPGA remains a stubbornly costly and power-hungry technology. One reason is the space taken up on a chip by the configuration transistors and the I/O which can leave less than half the total silicon area available for user logic.

You can get around this by using the anti-fuse FPGAs of Actel and Quicklogic, but then you sacrifice reprogrammability. None of the big programmable players see anything on the horizon, except incremental improvements, to change this state of affairs for the foreseeable future.

Meanwhile, all the logic producers, programmable and hard-wired, are having to face up to the power problem. Power no longer reduces with scaling which, in turn, means that performance cannot be improved.

John East

“We’re going to see fewer and fewer places where it makes any sense to shrink,” says John East, CEO of Actel. “FPGAs are going to 65nm next year, but 65nm will not be a smaller die than 90nm and it won’t use less power than 90nm, so the only benefit will be speed. But 90 per cent of FPGA applications are happy with the speed. So why are they moving to 65nm?”

“Some logic products don’t shrink at all. Some shrink less,” agrees Dr Wolfgang Ziebart, CEO of Infineon Technologies. “Fewer and fewer parts of the logic business are following the same rate of shrink as the memory business. If you look at the last two technology nodes, the share they took of production output continuously went down. Only 40 per cent of the products made used one of the two latest technology nodes.”

So, whereas a shrink used to provide the triple benefits of faster speed, reduced power and smaller cost, nowadays it does not.

Some investors even find it attractive to back older process fabs. “We are investors in CSMC which is an eight inch fab running 0.5 micron and 0.35 micron processes in China,” says Robert Jelski, global sector head for semiconductors and electronics at UK venture capital investors 3i.

Aart de Geus

Of course there are fixes for the power problem. One comes from EDA. “We can turn off at the transistor level, at the gate level, at a whole clocking domain level, at the whole sub-module level, and at the whole chip level,” says Aart de Geus, CEO of Synopsys.

The use of strained silicon, silicon-on-insulator and silicon germanium can all help alleviate the worst effects of the power problem and it is possible that a new material will be developed which could solve the problem.

“All the people who work on that say: ‘Don’t count on us to reduce power loss,” says de Geus. Intel says it has such a material, and is keeping it secret, but that has not persuaded the company to give up on its multi-processor strategy which was its initial response to the power problem.

So the ideal logic chip remains some way off. Designing at the system level with an unlimited power budget would be a fine thing, but it is not possible now.