Dominic Plunkett explains why the increasing use of BGAs is fuelling a surge of interest in boundary scan testing among board designers and test engineers.

Modern JTAG test systems are an effective answer to today’s test challenges, particularly as modern boards tend to be small and densely-populated, and feature increasing numbers of ball grid array (BGA) chips, such as FPGAs. The number of JTAG-compliant components on the market today is also increasing, and engineers can exploit this by using powerful tools to achieve high test coverage without requiring physical access.

The question of how to test complex, feature-rich boards has challenged generations of product developers and test engineers. Intense competition in modern markets is now putting pressure on engineering costs and time-to-market, demanding that development and manufacturing engineers not only maximise test coverage but also speed up prototyping and debugging, reduce test development time, and improve fault detection and rework.

The increasing use of ball grid array chips is contributing to a surge of interest in boundary scan testing

However, today’s very high component densities, combined with growing use of area grid array type packages, including BGA, micro-BGA, chip scale packages (CSP) and direct chip attach, make this difficult, particularly as they preclude access for test fixtures or probes.

Engineers can no longer rely solely on test techniques that require physical access – from buzzing-out development boards to bed-of-nails testing on the factory floor. But boundary scan testing can offer an answer to these challenges. The latest generation of JTAG testers allow a high proportion of a board to be tested, present test results in sophisticated graphical formats, and also simplify and streamline development of test scripts to exercise these increased powers.

The availability of JTAG compliant chips is also steadily increasing, as chipmakers acknowledge JTAG’s ability to solve the problems facing engineers.

With increasing numbers of JTAG compliant variants of commonly used devices – such as ASSPs – on each board, engineers can significantly increase boundary scan test coverage. Some JTAG test systems go further, by using the JTAG chain to manipulate non-JTAG devices on the same net, and thereby gain valuable additional test coverage.

By combining the boundary scan description language (BSDL) files for JTAG-compliant components with test scripts written for each device and the board netlist itself, the XJTAG boundary scan system, for example, calculates how to manipulate the JTAG chain in order to access as many nets as possible, including those with non-JTAG devices. Board design changes can easily be accommodated by recompiling using the revised netlist, making JTAG a powerful development debugger as well as a production test solution.

Hansatech, a contract manufacturing partner to a number of high-tech brands, says that several of its customers have invested in boundary scan for development work, which allows engineers in both organisations to work together to produce development test programs and subsequently optimise them for production purposes.

Another advantage of this device-centric approach to boundary scan testing is that the BSDL files and test scripts for a particular device can be retained and then re-used each time that device is used in subsequent projects. Designers and manufacturers can build up large libraries of proven tests for commonly used devices.

By quickly ‘productionising’ programs developed for engineering assessment, and by re-using device-centric test scripts, the non-recurring costs of delivering a test solution can be significantly reduced. Furthermore, these costs can reduce further as the libraries of functional test routines held within the organisation continue to grow.

It is also possible for engineers using modern JTAG test equipment to view the status of each pin graphically in real-time, via a powerful GUI. Hence, the behaviour of circuits incorporating large numbers of BGA devices can now be visualised in much the same way as using a logic analyser. Individual pin states and pin values can also be toggled easily.

Contract manufacturers, such as Barric, are early adopters of JTAG test solutions. Pictured is Sarah Green, test engineer at Barric, using the XJTAG system

As an example, contract manufacturer Barric, has found circuit visualisation using JTAG to be valuable as a quick way of checking for component and manufacturing defects in prototypes and pre-production samples. By quickly loading BSDL files and viewing a full on-screen representation of the states of all the balls of each BGA device on a customer’s prototype board, engineers detected that light pressure on one of the BGAs changed the states of the signals on some of the balls. In this way, they were able to trace the problem to a faulty junction between the substrate and silicon of the device itself. These types of faults commonly take hours to diagnose, but can now be located and identified within a few minutes using a boundary scan test.

Another advantage is that engineers can interact with the board at a very early stage of hardware development, without first having to debug the processor/memory system or program devices. Basic functionality can be quickly verified, and bridges, breaks, poor joints or incorrect connections located, as soon as the first prototypes return from assembly. This can be accomplished more quickly than buzzing-out the board. The results can also be easily recorded for future reference, and users can quickly and easily repeat any or all of the tests for a board, to enable them to track down a fault.

Further enhanced capabilities also help with hardware-software integration. For example, it is now possible to step through or over test code a line at a time while controlling the device through the JTAG port. Breakpoints can also be created and edited, and the values of variables in the code can also be checked or modified. Engineers can also control device operational modes and read registers, which allows power supply rails to be verified and monitored relative to desired limits without physically probing the PSU outputs.

JTAG tests can now be easily integrated with the majority of production test equipment, including in-circuit test (ICT), flying probe or functional testing.

When writing functional test software, in C or VB for example, engineers can simply call up a device-centric JTAG script, and then pull the results back into the main functional test application code for validation and reporting.

This can be achieved using quick and simple programming, and without requiring API calls to third party software. JTAG can now form part of a hybrid test strategy using a combination of these approaches, and contributes quick, net-level verbose diagnostics. In this way, electronics manufacturers find they can achieve significantly higher yield for prototype batches and early production runs.

On many boards, especially those designed for boundary scan testing, JTAG can now provide the sole test strategy.

With physical access to component I/Os and even test points now receding rapidly, engineers must look beyond conventional test techniques in order to achieve adequate test coverage for complex boards in modern wireless, networking, telecommunication, aerospace, automotive and consumer products. A device-centric approach to boundary scan testing unlocks the door to a practical answer, particularly now that JTAG compliant ICs are becoming more commonplace in chipmakers’ catalogues.

Dominic Plunkett is chief technology officer at XJTAG

www.xjtag.com