IDT (Integrated Device Technology) has unveiled a network co-processing device that aims to offload statistics tracking from network processors, FPGAs and Asics.

Described as the industry's first off-the-shelf statistics engine, the device targets edge routers, broadband access equipment and multi-service provisioning platforms.

The device connects to the main processing units via a look-aside (LA-1) interface to the Network Processor Forum (NPF) standard.

According to IDT, designers using the statistics engine can focus on other compute-intensive tasks, such as meeting the requirements of IP-based services, including the transition from IPv4 to Ipv6 and the deployment of content-rich services.

"With today’s internal processing elements operating in excess of 1GHz, stalling on multiple external multi-clock read cycles per packet for flow statistics is very costly," said IDT. "Stalls often require processor threads to context switch, further adding to complexity and overhead, which can exceed design budgets."

By using a 64-bit ALU to offload processor tasks, the engine can remove 90 per cent of the statistics tasks from the main processor. The ALU can also be configured as a 32-bit device to support legacy systems.

"By preventing the processor element from stalling on the restrictive external bus transactions, the IDT statistics engine will play a critical role in helping customers overcome system-performance challenges," IDT added.

A key part of the device is called the 'fire-and-forget' operation. This replace the more usual read-modify-write mode of operation. The benefit is that the processor can access and update four counters per clock cycle, while saving bandwidth on the memory interface.

A multi-port memory interface "ensures coherency for low latency statistics operations that require multiple statistics updates every five nanoseconds", said IDT, which it said is important in 10Gbit systems.

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