Debug specialist Novas Software has released two products to speed up verification and debug by improving visibility into complex SoCs.

Scott Sandler, Novas CEO, said the key capability in the Siloti SilVE and SimVE ASSPs is in correlating the representation used in emulators with up-front RTL.

“Verification breaks down when a bug is detected,” he said. “The whole team runs around trying to figure out what to dump… A no-dump simulation takes fives times as long as a full-dump run. By dumping a selected set of signals for the entire design it can be only x1.2.”

Early in a design cycle it is possible to find out what is happening inside a chip by dumping as many signals as needed, but nearer completion the number of signals to be dumped is computationally prohibitive.

In emulation, prototype, and actual-chip situations access to signal data is achieved via logic blocks in the hardware, making visibility even worse.

The Siloti products tackle this by compiling the HDL design and analysing it for essential signals, which can guide the later data acquisition process.

Specialist engines then map the low-level structures of the chip up to the RTL, and “expand the dumped data to fill in the gaps for full visibility”.

www.novas.com