The news that Xilinx has demonstrated first silicon of its 65nm next-generation Virtex FPGAs and delivered software to key customers does not mean that 65nm devices are about to flood the market. Nevertheless, it represents an important stake in the ground and raises some questions about what we can expect from the technology.

What we know at this stage is that Xilinx’s 65nm process uses an exotic combination of triple oxide technology, mobility-engineered transistors and something called Nickel Silicide self-aligned technology, all of which work together to minimise leakage current, which is the bane of these ultra-deep submicron processes. The 65nm devices will have a 1.0V core, rather than 1.2V as in the 90nm family, and an extra level of metal for routing.

Xilinx’s 65nm family will continue along the same functional lines as the current Virtex-4 ‘domain-optimised’ devices, with three FPGA types in the family geared towards DSP, logic and embedded domains (as in the current LX, SX and FX devices) using different mixes of logic, memory, DSP, serial I/O and processor ‘slices’ integrated on chip.

At 65nm, the technology is there to double the size of an FPGA and to double the performance, according to John Heighton, Xilinx’s product solutions manager for Europe. “But the issue is at what cost and at what power. So what we’re trying to do is find the right balance. We don’t want to produce a white elephant,” he says.

Increased density

Heighton is only prepared to reveal that the family will offer an increase in density greater than ten and less than 50 per cent. “The fabric will be faster too, but not twice the speed. The power consumption won’t be more than the 90nm devices, but we’re not exactly sure what it will be at the moment,” he adds.

The largest current Virtex-4 device, the LX200, would be able to accommodate something like a high definition H.264 encoder, an application that might require 12 to 20 discrete DSPs. So one could expect the largest 65nm devices to provide a capacity equivalent to up to 30 DSPs.

Xilinx’s closest competitor, Altera, has not yet made a 65nm announcement, but it plans to have software later in the year and to roll out silicon in 2007.

Pat Mead

Pat Mead, Altera’s senior manager for product and corporate marketing, explains some of the challenges of moving to 65nm. “People have got used to power gradually decreasing over the years as the core voltage reduced. When we get to 90nm and 65nm, leakage current and therefore leakage power start to play a significant role in the equation,” he says.

“People have been used to their logic density doubling and the power going down with a new process technology, but we’re in the generation where if you do nothing but double the density, you can also expect the power to increase. The challenge with 65nm is to make sure that doesn’t happen.”

However, 90nm has plenty of life in it, says Mead. For example, last week Altera shipped its first 90nm Stratix-II GX devices with embedded transceivers. With up to 20 low-power transceivers operating between 622Mbit/s and 6.375Gbit/s, these FPGAs can support every high-speed protocol you could think of.

“For existing protocols, there is a lot of headroom but for next-generation protocols such as PCI-Express and Serial Rapid I/O in the 5Gbit/s region then this a device that will allow you to implement those,” says Mead.

For users such as Nallatech, which makes FPGA-based computing systems, 65nm FPGAs cannot come soon enough. “As long as we’re producing multi-FPGA systems, FPGAs aren’t big enough,” says Malachy Devlin, CTO of Nallatech.

Power problems

Powering these leading-edge FPGAs, however, is becoming a headache because of the low voltages, tiny tolerances, increased noise sensitivity and high currents. “In a synchronous design, you end up having these great current surges coming through,” says Devlin.

“We’re also getting less I/O because there are more pins being devoted to the power and ground. It is not unrealistic for us to have a dozen power supplies going into an FPGA. Five years ago, you might have had two power supplies.”

Devlin would ideally like next-generation devices to offer more sophisticated support for partial reconfiguration.

“There are tools to do it but not at the speed required in a computer. I would like to compress what we do on multiple FPGAs into single devices. I want to be able to leave the I/O in place and change everything inside the FPGA,” he says.

“I would like to be able to switch in different operators – change an adder to a multiplier, for example – on a cycle-by-cycle basis. For high-performance computing, if I have only one large FPGA, one user could implement his algorithm in half the FPGA and with partial reconfiguration, a second user could use the other half.

“The bigger FPGAs become, the more we need to do this, otherwise you’re wasting space as the algorithms will be using only a fraction of the chip,” Devlin points out.

The idea of next-generation SRAM FPGA implementing more of your system sounds attractive unless, of course, your system runs on batteries and then the concept falls on its backside. For those looking to mop up system functions in handheld and portable systems, the leading edge is represented by less glamorous non-volatile anti­fuse and flash FPGAs.

Antifuse breathes new life

Last year QuickLogic introduced the 180nm PolarPro antifuse architecture for portable electronic systems.

PolarPro combines FPGA logic with embedded circuitry for implementing high bandwidth bus-to-bus interfaces, including large arrays of on-chip dual-port RAM with co-located asynchronous FIFO controllers, DDR interfaces for memory expansion, and clock management units. All device circuitry is optimised for low power usage through the very low power (VLP) mode.

“As functions get added to the portable market, there seems to be quite a problem in power management in connecting all the different peripherals and interfaces and even some of the chips together,” explains Owen Bateman, sales director of QuickLogic Europe.

“VLP, for example, allows us to isolate the internal FPGA logic from the I/O ring so we have in-built weak-keeper circuitry in the logic cells. It provides a weak logic level into the array while isolating the array from the logic pins. The logic is held in a known state.

There is an external pin that takes you in and out of this mode. Entering into the mode is instantaneous. To exit it takes 250ns to stabilise the clock,” says Bateman. In this state, the FPGA device will consume less than 10µA of inactive power, regardless of I/O activity.

Flash - the new kid on the block

In January Actel started shipping its Fusion flash family devices, 130nm programmable system chips that integrate mixed-signal analogue, flash memory blocks and FPGA fabric.

Martin Mason

“We are seeing Fusion being used in the system supervisory role, doing power management, thermal management, communication and control of the system, data logging of events in systems, test, bridging between boards,” comments Martin Mason, Actel’s director of silicon product marketing.

"It allows customers to take ten parts of their board and put a single programmable solution in place.".

“There is a lot of speculation about 65nm technology and in particular the issues surrounding power consumption.

"There is clearly an opportunity for power optimised and low-power FPGA technology. There is the need for very small form factors and the non-volatile technologies lend themselves very much to that space,” he concludes.

www.actel.com
www.altera.com
www.quicklogic.com
www.xilinx.com