CMOS will remain the chip process technology of choice for performance and cost for decades to come, according to a senior technologist.

Gene Frantz, Texas Instruments principal fellow in the DSP group, said that despite the huge advances in CMOS process and device technology in the last ten years, silicon technology is still well below the theoretical limits.

He believes silicon will continue to be the leading edge semiconductor technology for many years.

“Silicon is still the technology of choice and will be for many decades where cost is an issue,” said Frantz, who was speaking at TI’s European Developers Conference in Birmingham.

The theoretical limit for transistor gate length on silicon is around 1.5nm. “If you take a 65nm CMOS process today it has a minimum gate length of 39nm which is still 25 times larger than the theoretical limit,” said Frantz.

It is a similar story for gate delay, which determines the fundamental speed of the logic. The theoretical limit is 0.04ps which is 24 times shorter than the delay achieveable in today’s 65nm logic devices.

In terms of transistor density, that is the number of device which can be squeezed on to a chip, the limit is 1.5 billion per cm². This is a factor of seven larger than what is achieveable on a 65nm CMOS device.

Frantz believes we may no longer be able to use Moore’s Law to predict when CMOS technology will approach its limits. Performance is no longer simply an issue of clock speed, but also the degree of parallelism in the architecture.

“Performance as measured by clock speed fell off Moore’s Law a decade ago,” said Frantz.

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