In this week's Q5, our five quick questions to industry leaders, we spoke with Walden Rhines, chief executive officer of EDA firm Mentor Graphics. He has previously been the executive v-p of Texas Instruments’ semiconductor group.

Why did you choose to join the EDA industry?

Actually, I had a fairly onerous “non-compete” agreement with TI that prevented me from joining another semiconductor company.

But EDA was a logical place for me. Design has always been the most exciting part of the semiconductor business for me because that’s where the largest share of innovative differentiation begins.

With manufacturing challenges getting tougher, what’s happening to the traditional “throw it over the wall” mentality for designers and for manufacturers?

Wally Rhines

A revolutionary change. Manufacturing complexity, resolution enhancement technology and the need to take manufacturing process variability into account during the design finally became so important for achieving competitive tools that a whole new array of EDA design capabilities were adopted.

For Mentor, this has had a major impact on our revenue and on the nature of our development programs.

The VHDL standard is popular in Europe. What do you think will be the impact of the rise of System Verilog on VHDL?

System Verilog is a great language that facilitates testbench development, assertions, coverage-based verification and other aids for effective design methodology. That doesn’t mean that existing languages will be abandoned. People have become used to doing mixed designs, and are likely to continue doing so for a long time.

The most likely scenario is that open languages that are sourced by multiple EDA suppliers, like Verilog, System Verilog, VHDL, and System C will continue to be used while sole source languages like “e” will gradually fade away.

Are we really taking less time today to complete designs than we used to?

There’s no doubt that product development cycle times have been reduced dramatically - just look at the time between each manufacturer’s mobile terminal introductions. New methodologies have more than offset the time required to deal with the increased complexity of design and verification at 90nm and below.

You seem to have spent more time in the UK and Europe than most EDA executives. Why?

European companies tend to take a system perspective into design. But, because of my TI history, I’ve also been friends with lots of UK electronics leaders for more than a quarter century - people like Sir Peter Bonfield, John Scarisbrick, Rob Wilmot, Peter Van Cuylenberg and many more. Knowing them led to more associations and a close involvement in entrepreneurial activity in the UK.

Mentor Graphics