TSMC has announced it is open for volume foundry business at the 65nm node with a low power version of the process and other versions will follow.

“Volume in the foundry business means that you’ve worked with three to five customers with ‘risk production’ on six to nine designs and have come up with yields that are satisfactory both to the customer and to the foundry,” Chuck Byers, director of brand management at TSMC, told EW.

“What we’re saying is we’re open for business at 65nm. It’s ready for volume production and we’re open to purchase orders,” he said.

One customer which has announced that it is producing samples for customers on the 65nm process is Qualcomm which is using it for its 3G modem chip samples.
Apart from a change in the silicide material from cobalt silicide to nickel silicide, there are minimal material changes in the process.

“It’s our third generation of copper interconnect and third generation of low-k dielectric,” said Byers. The stability in the materials is what has contributed to a reasonably smooth transition from 90nm to 65nm.

This change in the silicide, and a drop in voltage, help to deliver a process which has similar standby power, and reduced active power, compared to TSMC’s 90nm process. The big benefit in moving from 90nm to 65nm is that 65nm delivers a doubling in the transistor count.

Risk production of TSMC’s high performance version of its 65nm process is scheduled to start in mid-Q3. It is expected that this is the process which Altera will be using for its first 65nm product, the Stratix III.

Following the launch of the high speed process, a general purpose process will be introduced.