A consortium of firms spread across the chip industry is proposing a new standard that promises to automate low power chip design.
The Power Forward Initiative has been set up by Cadence, and the official list of PFI collaborators includes AMD, Applied Materials, ARM, ATI, Freescale, Fujitsu, NEC and TSMC. However, there are other firms not yet confirmed, and they include some of the biggest consumer electronics and chip companies.
"We see that collaboration is no longer one-on-one, so we set out with the major goal of getting representation across the chain," said Jan Willis, senior v-p for industry alliances at Cadence.
While logic and timing have standard formats for passing data between design tools, power has no such luxury.
"Unlike the functional or timing worlds, it is very difficult to automate low power design," explained Eric Filseth, v-p of product marketing at Cadence.
Today's methods of capturing design intent for low power are either manual or use proprietary interfaces. The PFI consortium is proposing a new data standard, called Common Power Format, that will allow EDA tools spanning design, verification and implementation to run off that common data.
Willis said the PFI will be open to any firm, and that it hopes to place CPF as an open standard with groups such as the IEEE or Accellera within two years.
"We've been very thoughtful in doing this, so it doesn't take 15 years to get a standard," said Willis.
The PFI comes just one year after Cadence launched the Silicon Design Chain, an industry consortium which also aimed at improve low power design.
Willis confirmed that PFI will take over from the previous initiative. "This helped us prove some of the key methodologies," she said.
The Silicon Design Chain also failed to include the user community, which PFI will address, added Willis.
Cadence