Phil Hester, senior v-p and chief technology officer at AMD, sat down with Electronic News to discuss future market opportunities, strengths and weaknesses in AMD’s lineup and what’s changing inside the company. What follows are excerpts of that interview.
Electronic News: Does AMD have any plans to move beyond the desktop, server and mobile world into the embedded market?
Hester: Different people define the embedded space differently. If you look at the very low end of the embedded space there’s a class of devices [like the iPod] that has a proprietary embedded operating system and a fairly limited set of applications. There are a whole boatload of architectures that are successful there—ARM, PowerPC, MIPS, SH3, SH4. There’s not real value trying to push x86 in those markets. As these devices get more sophisticated and become more general purpose, the clear message we’ve gotten is a general-purpose software development and execution environment adds a lot of value. There’s a class of device that will merge between [the iPod] and a general purpose notebook that will be able to run a range of applications—not a predefined set—and can take advantage of x86. In that space, absolutely, it will be embedded x86. There’s a very low end space, below that, where it’s questionable whether x86 will add value. In this emerging space below notebooks, in what some people call a ‘brilliant’ phone—somewhere between a Blackberry and a notebook—absolutely. But there is always going to be a lower end space where a specific embedded architecture does just fine.
Electronic News: There’s a whole new emerging class of computing devices that use technology such as retinal reflection. Would AMD play in that space?
Hester: Yes, because that would run a general purpose software stack. We would talk more about where it fits by the application rather than the form factor.
Electronic News: One of the more interesting ideas to come out of AMD recently was the idea of allowing third parties to develop IP or separate chips that work with your processors. Will third party technology migrate onto the processor itself?
Hester: What we’re doing right now is putting the infrastructure in place to let that sort of migration happen. If you ask specifically which cores and when, that’s something I can’t predict. For a long time, in the PC space, there was a separate floating-point co-processor. In a transition from the 386 and 387 to the 486, enough of the applications were using floating point that you could justify the incremental cost of adding in that silicon capability. A high enough fraction of users needed both pieces so the economics of that worked. Today if you look at these vertical markets—Java, XML, vector floating point media processing—those don’t yet justify everyone incurring the cost of that silicon. The right answer today is to enable, with as little incremental cost, these vertical systems to be built. What we want to do is to give a migration path so that when those application accelerators do make sense we’ve got both the systems architecture and the internal co-processor architecture designed to let those co-processors live all the way from being attached on PCI Express or HTX today to potentially being an execution unit on the main die. I’ll speculate, based on history, at some point that will happen.
Electronic News: So instead of AMD doing battle with Intel, it’s now AMD plus its allies?
Hester: I don’t know if it’s as much doing battle with Intel as it is to naturally expand the capability of these systems. If you talk to the companies that today are building the Java or XML accelerators, what they have to do is build a whole system—both hardware and software—just to deliver that accelerator. That’s typically what we refer to as ‘N plus 1.’ The N is the general-purpose servers that don’t go away. You have this one thing that accelerates particular applications. What you ideally want is a base system that can run the general purpose applications extremely well that only have to incur the development expense of the accelerator piece, not go build this whole system from the ground up. To me it’s a very efficient way to satisfy what some of our end customers and some of our OEM partners are telling us they want in the way of capabilities for these future systems. That way they can spend their dollars optimizing their systems, not replicating the things that Opteron already does well.
Electronic News: Is it more efficient, though, to have functions on the chip or off the chip?
Hester: If you’ve architected from the ground up, it’s more efficient to do it on chip. The reason is that you have fewer chip crossings and fewer I/Os. Driving across a chip boundary into a printed circuit board is always going to take more power than driving a bus inside a microprocessor. If you look at the system level, some of the absolute power savings may be relatively modest compared with the amount of power the whole memory subsystem uses. Externally, there is always some additional cost in terms of efficiency. That may be relatively minor, but you clearly can do the ultimate optimization when you put it on silicon because you have direct control over all the elements that you need to.
Electronic News: IBM, one of AMD’s partners, is now doing system-wide design to optimize power and performance. Is that starting to happen for AMD, as well?
Hester: AMD is part of the consortium relative to co-technology development. Normally it’s driven out of the mobile space, not the desktop or server space. For power efficiency, it’s not just the CPU, which we control, but also the Southbridge I/O chips. For example, we are working with memory technology companies, looking at what the power requirements really are. The short answer is we’ve been doing it and we will continue doing it. When and if it makes sense to put it on the die, we have put together a next-generation architecture that will let us do that.
Electronic News: Is there a practical limit to how many cores can be used in a processor?
Hester: In the server space, the large RISC Unix machines run upwards of 64- to 128-way processors today. It has been shown that the applications that work on those have been tuned to an SMP [symmetrical multiprocessing] format. On the server side, there is not a lot of limitation. On the client side, I’m going to give you two answers. One is that had you asked me that a year ago, I would have been a lot more pessimistic than I am now whether enough interesting applications are going to be multithreaded. A lot of that has been driven by the gaming community. If you look at what’s happening with Xbox 360 and the upcoming PS3, that’s forced a lot of the game developers to start thinking multithreaded. As they architect the internal structure of those games, many of them also want those same titles to run on a PC platform, so we’re getting some indirect benefit. That’s what drove us to do a ‘4 x 4’ chip. Had you asked me a year ago, I would have said you wouldn’t get there really quickly. If you ask about eight cores on a client microprocessor, part of the reason we’ve done this modular design is to be able to make that decision much later in the design cycle than what we would have done historically. Part of the reason is that we have to understand what the workloads will be and what the typical usage will be in the client space. That is clearly evolving. Very few, if any, software developers outside of the gaming community thought multithreaded for the past 20 years. There are only so many threads a single human can drive on his PC.
Electronic News: There also are only so many they can program with the current compilers, right?
Hester: The folks at Microsoft Research are doing some work on a multithreaded software environment. We have had this discussion with them a number of times. Part of the reason we opened a Linux development center is to try to figure out how to do this with Linux. It’s a real problem.
Electronic News: Isn’t this the same reason the microkernel concept failed years ago?
Hester: Yes. It’s a very good question, particularly for the microprocessor where the die size is really precious because of the cost-sensitive nature of the clients. Are four cores and a good cache better than three cores and a really great cache? The answer to that is going to be driven largely by how fast the software technology evolves.
Electronic News: One of the other problems is that the development tools available today can’t do everything necessary to make this all work. Does AMD still develop its own tools, or does it buy everything from EDA companies?
Hester: It’s probably a hybrid of both. We have a good relationship with most of the major tool vendors. We don’t want to create tools that we can get from the industry. That’s not a good use of our resources. Today there’s a standard set of tools that we can get that are fairly effective. It’s at the integration and verification level that we end up developing our own tools. More and more we’re going to a distributed development environment. We have design engineers in Boston, Austin and Santa Clara. We’re adding a design center in Fort Collins, Colo. We’ve got one in Dresden, Germany. We have tools to do that. So it’s not that difficult to expand it to someone on the outside. Part of that would require education. There’s the standard Cadence/Mentor set of tools, and part are tools we’ve developed. I don’t see it as a huge challenge. It’s hard work. But we have existence proof among five sites that we know how to do distributed development.
Electronic News: Any plans to commercialize your tools?
Hester: No, we don’t have any plans to get into EDA tools. There are internal technologies we use to gain value at the chip level. These are tools we use ourselves.
Electronic News: Let’s swap topics. What are the new markets that are going to drive consumption of AMD chips that are not there today?
Hester: The one that I’m personally excited about is this thing we call ‘innovative systems.’ I’ve been looking at this for about the last six months. The perception is that a lot of people in developing countries want a low-cost, simple PC. There’s a certain amount of truth to that. But there are two other elements. A number of folks want really good technology for their family, but they want it to be more affordable. There’s a set of hardware technologies we need to build into chips into the future to allow alternate business models to be able to create these PCs more affordable. It’s not that you’re going to put lower-end technology in it. It’s technology that would allow subscription models, advertising subsidies, and pay-per-use models. It’s internal plumbing stuff from a silicon standpoint, but it’s very significant in terms of the new business models it allows you to support. That’s one area. The other area is driving down super-thin mobile cores beyond the ultra-thin, ultra-light notebooks we have today. Both of those are very exciting new spaces.
Electronic News: Where does the Moore’s Law road map end for AMD? You’ve already got a plan for 32 nanometers. What comes after that?
Hester: Realistically, in this industry when you try to look out beyond three to five years, the probability of you being right is almost zero.
Electronic News: But we’re also starting to run into some fundamental physics barriers. Is it better to design from the top down, using our standard silicon manufacturing, or do we grow it from the bottom up?
Hester: For the design cycles I see coming to market through 2010 or 2011, the current technology will be fine. There will be fundamental physics issues, as you say, involving individual atoms. So at some point, there will be a transition. But my history in the industry says that every time someone predicts a wall, someone else makes the wall go away. I remember 10 years ago hearing that we were going to hit the limit. At that time it was 2 microns. I have confidence in the innovation of the industry.
Electronic News: As you go down this path, your work with partners becomes even closer. How does that affect your business?
Hester: It’s an extension of what we’ve been doing. If you look at AMD’s history, we never had the view that it controls the entire stack, whether it’s hardware or software. We’ve always had hardware and software partners. I don’t see that fundamentally changing. The partitions between the individual components will change, but you’re still going to have to collaborate like you did in the past. At some point could you think about IP macros that fit in with our tool set so we fab it on the die—that’s a form of the collaboration we do today. Is it more complex in the future as you think about tighter levels of integration? Yes, it is. But it’s also a natural evolution.
Electronic News: Some of the most innovative decisions being made these days are on the business side of the operation, including your own Terazza model for working with partners. How does that affect the technology development?
Hester: I would say a fair amount. If you take a look at what we’re doing in developing geographies, the way a PC is typically bought in developed countries is not going to be the way it’s bought in developing countries. If that’s the customer you’re trying to satisfy, the way you go about that is to enable a business model. What is being heard loud and clear by the engineers is the customer-centric message. Megahertz for megahertz isn’t going to do it. What’s the real value that we’re going to create with the silicon? That’s being heard by the engineer.
Electronic News: One last question. If you look at your strengths versus Intel’s, where is AMD strong and where does it need to grow?
Hester: If I look at where we’ve been historically, we have focused on one-core microprocessor design that we could modify to serve the desktop, server and mobile markets. Opteron’s heritage was really out of the server and performance desktop space, and mobile was not a priority. Moving forward, we will have two centers of mass for our design. One is a scalable power-performance RAS [remote access server] design for the server space that also meets the upper end of the desktop. Going forward, the mobility space is focused on better power efficiency than what we have today. We will improve in the mobile space, and also in the emerging geography space. I do feel good about the overall competitiveness of AMD. The design cycle from the time we introduce a new technology to the lead time the OEM needs, depending upon the complexity of the platform and how much technology besides the microprocessor changes, is six to 18 months. The more design wins we have the more we gain market share, and we continue to gain more and more design wins.
Electronic News is a sister publication of Electronics Weekly