Altera is using encryption and a non-volatile security key to allow designers to protect their IP in Stratix II FPGA designs.

The firm said it is responding to a trend which is seeing designers using FPGAs to perform critical system functions that were traditionally filled by Asics or ASSPs. It is using the advanced encryption standard (AES) along with a 128-bit non-volatile key for IP protection.

According to David Greenfield, Altera’s senior director of product marketing for high-end FPGAs, very few if any high-performance FPGAs support non-volatile design security. “Stratix II FPGAs deliver a secure approach that protects proprietary designs and IP using bitstream encryption, providing clear differentiation for customers looking to protect their IP investment,” said Greenfield.

The Stratix II design security solution allows different security keys to be programmed into different Stratix II devices, enabling product version control and customization. The ability to encrypt configuration files in Stratix II FPGAs should protect royalty income for IP vendors, since they can track exact IP usage.

The tampering protection of the Stratix II design security solution prevents undesired modification of gaming machines.

Another feature is that ASSP vendors can test market and adapt the functionality in their ASSPs via Stratix II FPGAs while protecting their IP.

A user-defined AES key can be programmed into the 128-bit non-volatile key stored in Stratix II devices. The same key is used by Quartus II design software to generate an encrypted configuration file stored in an external memory or configuration device.

At power up, the memory or configuration device sends the encrypted configuration file to the FPGA and the device then uses the stored key to decrypt the file and configure itself. This Stratix II AES implementation is FIPS 197 certified.

These new security features for Stratix II GX will be available in the third quarter of 2006.