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|NewsletterA chip that replicates the structure of the brain is to be built by a team from the University of Manchester, ARM and EDA start-up Silistix.
The chip will be used to investigate the computational activity of neuronal networks by running biological data derived by neuroscientists. It could have applications such as robotic control.
The three-year project is being led by Professor Steve Furber, the man behind the Amulet asynchronous ARM processor, and will use a patented communications infrastructure to mimic the signalling behaviour and adaptive topology of very large collections of neurons.
“You start with a static view of the connectivity patterns, but you build in the adaptation and try to reproduce the adaptivity of the biological system,” said Furber.
To do that the architecture needs to be able to scale over a large number of chips. Furber said it is impossible to use a broadcast technique to propagate signals, because it doesn’t scale. Instead, he is using a source routing approach (as opposed to destination routing) called ‘address-event communication’, in which each event has an address that describes where it came from.
| Steve Furber |
“The problem is one of a network that has very high fan-in and fan-out properties – neurons typically have 1,000 to 10,000 connections - and so if you do [these links] all with individual point-to-point you end up with lots of message replication,” said Furber.
“The communications [structure] uses a multi-cast algorithm, so a spike is issued as a single packet from the neuron that starts to spike, and it propagates through these chips. But where it has to spread out, the packet gets automatically replicated, and sent to all the necessary places,” he said.
The chips will be straightforward digital CMOS devices comprising large numbers of relatively simple processors acting as the model neurons. Transistor count will be around 100 million, and they will probably use UMC’s 130nm process.
Silistix, which develops a self-timed on-chip interconnect for complex systems-on-chip, is involved to help decouple the synthesised clocks on the various cores, to make it easier to achieve timing closure.