Just a few years ago a power supply was expected to produce 5V for logic, plus/minus 12V for analogue and maybe 24V for electro-mechanical components. It was switched on and off by a mains switch.
But several developments are adding complexity to the modern power supply. Most significant of these are regulatory requirements, foremost amongst which is a reduction of main current harmonics. Also of regulatory origin is the requirement for low-power stand-by modes; in some markets the requirement is a maximum 1W power use in stand-by. Another requirement is to limit mains in-rush surges when the supply is connected.
On the output side, modern applications are requiring more output rails, frequently with specified start-up sequencing and interlocking.
All these developments add complexity to the design, increasing component count and raising new issues of interoperability between the various requirements.
Requirements for power factor correction (PFC) effectively make a power supply behave like a resistive load drawing a sinusoidal current in-phase with the mains voltage. This gives a pulsating flow of energy into the power supply. But if the power supply is producing DC outputs with constant loads this represents a constant energy release and the implication of this is that the power supply must have internal energy storage - normally a high voltage capacitor.
To achieve the sinusoidal current requires that input current flows throughout the mains cycle, even when the instantaneous mains voltage is low. To deliver this current into the high voltage capacitor requires a voltage boost and the normal topology of a PFC front-end for ratings above 50W is indeed a boost converter. To keep the boost converter active, the energy storage must be at a DC voltage in excess of peak mains voltage.
To produce the usual low voltage outputs from the power supply requires a conventional switch mode power supply working from the energy storage reservoir. The output converter now has a stabilised DC source of supply so it can be slightly de-rated, or more efficient, but there is still a double conversion of energy from mains through to load, which poses an efficiency challenge, and potentially leads to double complexity in the circuitry.
The double conversion architecture has two sets of switching devices, which are normally driven by two separate control chips. There are design challenges arising from no-load operation, start-up control and overload protection.
Universal input for the world market requires normal operation to range from 90 to 260Vac. This is impracticable with conventional design and leads to the adoption of the traditional manual switch selecting low and high voltage ranges. It is feasible to employ automatic switching from a bridge rectifier to voltage doubler to make the manual switch unnecessary, but this entails considerable complexity.
Low power standby needs an auxiliary supply to keep the standby circuit alive plus the means to shut down the main converter and usually an isolated control circuit for the start-up command.
A conventional power supply, employing direct rectification of the AC mains into a reservoir capacitor, draws extremely large inrush current surges when the AC mains is first connected. Negative temperature co-efficient (NTC) thermistors can provide good limiting at the first switch on, but are ineffective after short mains interruptions. A more thorough technique requires a power resistor to limit the current switching, such as a FET or thyristor to bypass the resistor and a means to control the switch.
Modern applications frequently have specific requirements for various voltage rails to start-up in correct sequence and specified timing. There are also requirements for over-voltage protection and voltage monitoring. These features can add considerable complexity if based on op-amps, zeners and transistors, although there are special ICs available.
The modern generation of embedded processors provide on-chip peripherals directed towards real world applications such as power control along with considerable processing power. It is the PFC task which provides the leverage for incorporating the embedded processor. The control of the sinusoidal input current previously required analogue multiplier circuitry on the stand alone dedicated PFC chip. Analogue multiplication is a complicated function with inevitable performance limitations but it is a small task for a modern embedded processor.
Adopting the boost converter architecture for PFC makes universal mains input easy and seamless in operation, with nothing more than a rating penalty where components must be rated for maximum voltage as well as the high currents required at the low voltage extreme.
The processor can somewhat mitigate the ratings penalty by adapting the overcurrent protection limits to provide constant power over the voltage range. Start-up control of the double-conversion power supply and in-rush current limitation are easily handled by software in the one central processor.
Having adopted the embedded processor, the remaining monitoring and control tasks can be software based using multi-channel on-chip analogue-to-digital converters. Low power sleep modes with hardware and software control can address the 1W stand-by requirement although a low power auxiliary DC supply is still required to keep the processor alive when the main converter is shut down. Spare processing power can provide additional features such as history logging and maintenance alarms.
As product specifications become tighter in response to the increasingly demanding marketplace, the complexities facing power supply designers will only increase. Universal input, lower stand-by requirements and increasing regulatory requirements represent some of today’s challenges. In the future, these will no doubt be replaced by others.
In order to cater for this, an embedded approach will soon become the preferred design route. Processors specifically targeted at such applications are already available and are becoming increasingly bespoke for the configuration that designers are looking for.
As a result of going digital, designers will be able to offer customers added functionality and a better commercial end result, with cost advantages such as reduced component counts being one such bonus.
Nick Palmer is technical director at ML Electronics