System designers of telecommunications equipment can now benefit from the IDT highly integrated, single-chip solutions for network synchronisation circuits. The IDT 82V3000 family provides a variety of flexible, fully programmable and cost-effective, application-specific ICs targeted at wireless infrastructure and wire line; access; transmission and network core applications.

Key benefits include ease-of-use due to full compliance with telecommunication standards (Stratum level 2, 3E, 4, 4E and SMC), a rich feature set and programmability for high flexibility and reduction of board component count.

The purpose of the IDT 82V3000 family of integrated circuits is the generation and synchronisation of telecommunication specific clock signals, achieving clock redundancy and circuit protection, attenuation of clock signal phase noise and generation, and conversion of standard telecommunications clock signals.

Typically used on line cards and central timing cards, these devices use an architecture that combines digital and analogue PLLs on a single chip:

The digital PLL is designed to provide compliance to telecoms standards such as high frequency accuracy on Stratum level 2, 3, 3E, 4, 4E and clock jitter attenuation. It provides circuit protection through integrated clock redundancy, including hitless switching, clock frequency holdover and phase build-out

The analogue PLL converts clock frequencies, saving external components for frequency division and multiplication

Nine devices of the current WAN-PLL family support a variety of synchronisation solutions. The portfolio of WAN-PLLs consists of frequency-programmable devices and also fixed-frequency devices.

The programmable devices with up to 14 redundant inputs and up to 11 outputs, such as the 82V3288, are the most flexible IDT solutions. These are targeted for applications requiring flexibility in output frequency configuration and maximum support of circuit protection and redundancy.

The fixed-frequency devices are optimised for cost and board space in specific applications which have a defined frequency plan, require fewer protection features, or require a smaller number of I/Os.

IDT WAN-PLLs support three types of input clock sources: recovered clocks from STM-n or OC-n, PDH network synchronisation timing and external references. The wide input clock range covers telecoms frequencies from 2kHz to 622.08MHz, and frame signals of 2kHz, 4kHz and 8kHz.

The clock outputs can be configured to generate frequencies from 1Hz to 622.08MHz and additionally generate frame signals at 2kHz and 8kHz. The IDT 82V3255, 82V3280 and 82V3288 WAN-PLLs support T0 and T4 clock paths independently; other devices of this family are specifically designed to support the synchronisation on DS0 (8kHz), T1 (1.544MHz), E1 (2.048MHz) or OC-n (19.44MHz) timing signals.

The designer now has the choice of using devices with up to 14 inputs and 11 outputs (IDT 82V3288). Single-ended and differential I/Os such as AMI, PECL and LVDS are supported, with an automatic detection of the signal input voltage levels.

Each IDT WAN PLL device synchronises the internal DPLL to the selected input clock signal and provides phase and frequency locked output signals. The DPLL also monitors the input clocks for failures.

Dedicated hardware signals are asserted in response to clock failures such as frequency drifts, signal amplitude degradation and accumulated no-activity events from input signals. In the case of an input clock failure, the IDT 82V3000 family of WAN-PLLs protect the telecommunication timing system through an automatic or forced switch to a redundant clock source.

The clock switch complies with telecommunication standards such as those defined in GR-1244-CORE, GR-253-CORE, ITU-T G.812, G.813 and G783, by providing “hitless” output clock phase transition characteristics and holdover capability. In holdover mode, which is typical for applications with no redundant clock source present, the DPLL output is the computed average reference frequency.

The most critical parameter that is met by the WAN-PLL is the absolute holdover stability of 1.1x10^-5 ppm (IDT 82V3255, 82V3280 and 82V3288). For dedicated, high-availability timing designs, the IDT 82V3255, 82V3280 and 82V3288 WAN-PLLs support master/slave configurations for both serial and parallel redundancy configurations and protection from single chip failures.

The integrated jitter attenuation capability of the DPLL helps the system designer achieve low phase-noise clock signals without the need for external jitter attenuation components.

With a programmable DPLL bandwidth (0.5mHz to 560Hz) and damping factor (1.2 to 20), IDT WAN-PLLs are the most flexible components for timing designs in telecommunication systems, allowing for jitter attenuation of input signals and realisation of high-quality, precisely timed output signals.

HO=Holdover Mode; SD=Invalid Input Signal Detection; RIM=Reference Input Monitor; TIE=Time Interval Error Correction; HS=Hitless Switch Capability; PBO=Phase Build-Out Capability, Programmable PLL bandwidth and damping factor

Feature summary:

• Family of single-chip solutions for the generation and synchronisation of Stratum 2, 3, 3E, SMC, 4 and 4E compliant clock signals
• Meets GR-1244-CORE, GR-253-CORE, G-1377-CORE, ITU-T G.812, G.813 and G.783 criteria
• Contains ICs with a full feature set and dedicated, application and frequency-specific ICs
• Includes up to 14 inputs and outputs, differential and single-ended signaling, automatic level detection
• Input frequency support: 2kHz to 622.08MHz
• Output frequency support: 1Hz to 622.08MHz
• Frame signal support: 2kHz, 4kHz and 8kHz
• Circuit protection through redundancy support, including forced and automatic hitless switching
• Free-run, locked and holdover operation modes
• Holdover absolute accuracy up to 1.1x10^-5ppm
• Holdover instantaneous accuracy up to 4.4x10^-8ppm
• Analog and digital PLL architecture
• Support of T0 and T4 timing patch independently
• Master/slave configurations
• Phase build-out to minimise phase transients
• Supports phase absorption
• Programmable input-to-output phase offset adjustments
• External oscillator offset can be compensated (resolution: 0.0000884ppm; range: ±741ppm)

Applications:

• Synchronisation of clock signals in telecommunication systems
• ATCA and carrier-class telecom designs
• Line cards
• BITS/SSU clock generation and synchronisation
• SMC/SEC SONET/SDH system timing
• Access, core, transport and exchange equipment
• Wireless infrastructure (GSM, 3G networks)

Support:  

• For more product information, see: http://www.idt.com/?catID=58700
• Product samples and evaluation boards are available