Electronic design automation technology with the potential to dramatically speed the simulation of electronic systems has been unveiled by Synplicity.
The firm, which specialises in Asic and FPGA synthesis, said that by using modern large FPGAs, it can simulate designs at real-world speeds, without the cost and set-up times of emulation systems.
However, this is not just FPGA prototyping, promises Synplicity, but a technique that combines 
hardware acceleration with existing simulation tools.
According to John Gallagher, the company's senior marketing director, previous changes to simulation, such as multi-threading, assertions, formal verification and FPGA prototyping, have given only incremental improvements.
"Each of these is essentially a small part of it [the solution], but they all have limits and only address part of the verification problem," Gallagher told Electronics 
Weekly, "and frankly they are all too slow. Only FPGAs can transact at anything like real speed."
"The goal we have is to get a method that can transact at real world speeds and allows complex interactions to be observed and verified," Gallagher said. The ability to observe the internal states of a system is one of the downsides of traditional FPGA prototyping.
Thus Synplicity has taken prototyping, and modified it so the designer has full visibility of the design under test - giving the test environment the combined power of RTL simulation, emulation, and prototyping, claimed the firm.
TotalRecall works by adding a duplicate copy of the hardware into the FPGA(s) being used for testing, along with a large memory buffer to store all inputs to the system. The hardware/software is executed until a trigger point is reached, whereupon the memory buffer is frozen.
The replicated hardware is then used to run the contents of the memory buffer, copying exactly what happened during the first run and generating a testbench and data which can be used for debugging by conventional simulation tools.
"It's a fast forward button for the simulator to get to the interesting bit," said Gallagher, with all memory, states and nets visible to the simulator.
"This will probably double the number of FPGAs in the prototype hardware, but that's acceptable if you gain full visibility of bugs."
In terms of speed, Synplicity gives an example of a mobile phone, which can take days to boot in simulation, but takes a few seconds in FPGAs running at 20MHz.
TotalRecall can also be used to test assertions, which are normally too complex to be coded into hardware.
"Assertions are wonderful things; they are behavioural - the accumulated wisdom of the design team," explained Gallagher, "but they do have limits, so people leave them out because they slow simulation too much."
By synthesising the assertions into hardware, they can run at full speed - at the expense of some more FPGA hardware.
Synplicity reckons this is the first time assertions will have been synthesised. "Assertion languages such as PSL are unique and not easy to compile," said Gallagher, so the firm is developing a new compiler for the purpose of turning PSL and OVL into hardware.
Although no products have been announced, the firm said its TotalRecall technology has been looked at by a few key customers, and should be available "in the coming year".
"The magnitude of what this technology can achieve is so large we need to give more runway to the user community," explained Gallagher.
The firm is currently working with FPGA suppliers and prototype board firms, particularly in Europe such as Hardi and Nallatech.
Synplicity