On the heels of Synopsys announcing three tools for measuring verification completeness, a new startup called Certess will introduce itself this week with a product direction to help verification engineers measure their projects, methods and productivity.

The new company is headed by EDA veteran Michel Courtoy, who after being a vice-president of marketing at EDA startups, most notably Silicon Perspective, is now taking on the role of CEO at Certess.

“Verification completeness has been a very hot topic lately,” said Courtoy. “The reason there is such a push for it is that despite all the investment in verification, chips are still failing due to logic failure problems. One of the main causes of this is that verification engineers have no measurement of the quality of their work.”

Courtoy said that design engineers typically have the luxury of having backup from verification engineers, who catch the mistakes of the designers, but verification engineers don’t have the luxury of a backup.

“We’re introducing ‘functional qualification,’ which is the ability to certify that if there is a bug in your design, your verification environment could catch that bug. It’s the ability to go in and measure the completeness of your verification environment. Qualification is to verification, what verification is to design. It is the ability to provide feedback, the measurement the control of the quality of that process.”

At this point the company is merely introducing itself and is not yet revealing the nitty gritty details of its tool, which it will likely introduce sometime before the Design Automation Conference this June.

Courtoy said that the initial release will focus on functional qualification of dynamic simulation and testbench verification but future releases will expand the company’s qualification technology into static formal verification, as well.

The CEO added that the tool will help users with IP verification or more accurately what users commonly refer to “IP re-verification,” ensuring that that each piece of IP is functionally correct - is of quality - before it is implemented in a design. He said the tool will also help design teams with verification allocation. That is putting verification resources where they are most needed in a given project.

The tool will also help with methodology evaluation and the impact of adding a new tool to a verification methodology. Courtoy noted that management can also use the tool to evaluate their design teams and their verification teams (which may not be a popular feature with design and verification team members). “We’re talking to multinationals, who have teams in India, China, Europe and the U.S. and North Africa and they need to find out what all those people are doing,” said Courtoy.

Certess has been shipping code to beta customers for one year.

The company was founded by verification engineers Mark Hampton, Mel Gilmore and Joerg Grosse in early 2004. The company’s chairman is industry veteran turned venture capitalist Jacques Benkoski, former CEO of Monterey Design.

At this point, Certess is backed entirely by Index Ventures, and the VC firm’s founder and general partner, Giuseppe Zocco, sits on Certess’ board of directors. The company is based in Campbell, Calif., but its main R&D centre is based in Grenoble, France.