Why is analogue design so much tougher than digital design?

Both digital and analogue design are about making trade-offs, but in analogue design there are far more variables which are more interdependent and there are fewer EDA tool options for analogue designers than for their digital counterparts. These include speed, power, area, gain, bandwidth, power supply sensitivity, signal distortion and phase noise. Analogue design means choosing the optimal subset of parameters, which are generally dependent on the experience of the analogue designer.

Unlike the automated design rule checking (DRC) procedures of digital design, in the analogue domain the impact of process variations and parasitic effects creates an iterative and unavoidably time consuming design flow. The analogue designer uses at least three, if not five, corner models (TT, FF, SS, FS, SF) to assess the effects of process variations, requiring upwards of five times the number of simulations that might be needed for a digital design.

Even then, corner analysis is fundamentally limited. It does not help predict degraded performance due to device mismatches. Monte Carlo analysis assigns probability distribution to device parameters such as width, length, and resistance and to model parameters such as threshold voltage (Vth).

An analogue design must be repeatedly revised, SPICE simulations run and re-run, and the results re-evaluated to determine the optimal system. Furthermore, SPICE simulators are not as trustworthy as digital simulators. Layout is more complex in analogue design, requiring the consideration of second and third order effects, such as the piezoelectric nature of silicon. Analogue design does not lend itself well to functional verification.

Due to the variability in analogue circuits, devices and processes, general purpose analogue tools do not exist. At best, there are a few design-specific analogue synthesis tools. Ultimately, the analogue designer relies heavily on experience.

DFM and process variations
Design for manufacturing (DFM) is the current buzz in the digital world as device geometries shrink below 130nm. In fact, DFM has always been a way of life for analogue designers. They have always been obliged to pay attention to the realities of manufacturing process and parameter variations as the circuit is fabricated.

Design migration is difficult. Analogue circuits are less scalable, with no abstraction models. Further, analogue transistors operate in the ohmic region which can vary between process nodes. When an analogue design is shrunk, the topology and top level of the design may be maintained, but all devices in the circuit must be resized for the new process. This becomes more difficult for deep submicron processes.

Migration from foundry to foundry is approached with trepidation. Analogue circuits are fragile, more sensitive to variations in materials and manufacturing processes, and require more shepherding between foundries.

Foundries assist by providing a variety of models, the most popular being BSIM3 and BSIM4 (Berkeley short-channel IGFET models, available in the public domain). These models try to predict, based on equations reflecting the physics of the device, how a transistor will react in silicon.

The models have limitations, which become more marked at the smaller process nodes. For instance, only recently have some BSIM models begun to include the piezoelectric effects of material stress on Mosfet behaviour.

These transistor models have 50 or more parameters. Foundries set these values by creating multiple test chips and measuring specifications. Typically, the parameters are set for digital behaviour and may be less appropriate to analogue designs. Analogue designers, therefore, have to create their own test chips and set the parameters based on the transistor behaviour important to them.

Whether initiating a design into an original foundry partner, pursuing a vertical migration, or migrating the design horizontally to a new foundry partner, the analogue designer needs feedback to understand the feasibility of the process and the viability of the design. The concept of first-pass silicon is just not feasible in the analogue world.

Parameterised cells provide relief
Analogue design automation efforts are progressing. The use of ‘parameterised cells’ provides a jump-start to analogue design. These can be viewed as analogue versions of the standard cells used by digital designers, but instead of only a few versions of each cell, there are hundreds to choose from.

For example, an NMOS parameterised cell will generate the layout of an NMOS transistor with a specified width, length, and number of fingers. Since analogue designs work at the device level, these parameterised cells can help automate the layout of the design.

Many parameterised cells are now available commercially, allowing analogue designers to choose which they need to create themselves and which to purchase. Foundries frequently provide parameterised cells for basic devices, though often only supporting one EDA vendor.

The analogue design flow
The power of parameterised cells becomes apparent when you consider a typical analogue design flow, starting with the selection of a circuit topology. Transistor sizes and values for resistors and capacitors are assigned and the design is simulated. The device parameters are changed and simulated again until the desired performance is achieved.

The designer creates the layout by either hand drawing each device or using parameterised cells to generate them and connect them together based on the schematic. Next, the layout is extracted as a netlist with device parameter values and parasitics. The extracted netlist is then simulated and device values are tweaked for the target performance. Finally, the designer changes the layout to match the new schematic and again extracts it as a netlist. This process is repeated until the desired performance is achieved.

The ability to update the layout quickly during the extraction, simulation and tweaking processes can boost designer productivity. Typically, the changes to device parameters are small, so the newly generated layout usually fits into the area previously occupied by the earlier device. Schematic driven layout (SDL) is the term given to the approach to automate this design cycle.

A good SDL system should read schematics or SPICE netlists. It will generate all devices in the netlist that have layout generators based on their individual parameters.

Next, it will place all generated devices and any other cells in the layout. SDL should also assist in routing the devices by displaying flylines and keeping track of which routes are finished. This routing is generally manual, because it is manageable and extra care is needed when routing sensitive (high impedance) nodes. Different analogue designers have their own ways of adding symmetry and laying out the circuit.

SDL should also be able to handle ECOs or changes to the netlist. Typically these only consist of changes to the device parameters, but ECOs may also include adding in extra devices. In either case, SDL should be able to automatically regenerate those devices that have changed, while maintaining their original placement locations in the circuit.

Although the use of a proven design methodology that includes parameterised cells may not automate analogue design in the same way as digital design, it reduces the time needed to converge on the correct analogue solution.

Paul Double is founder and MD of EDA Solutions