The convergence of mobile phones and other consumer-driven devices such as PDAs, MP3 players, digital still and video cameras is progressing rapidly. Consequently, a classic engineering paradox has arisen: an ultra high-performance portable handheld device with extremely low-power consumption.

Moreover, as the amount of processing power increases exponentially, it has become inevitable for mobile handset manufacturers and design houses to start adopting dual processor architectures. With the high data rates inherent in 3G/3.5G wireless systems, the bandwidth and latency of processor interconnects have skyrocketed in order to accommodate the requirements of multimedia features.

In today’s dual processor designs, the processing elements are typically a baseband processor and a function specific co-processor, such as an application or multimedia processor.

The two processors operate independently with the baseband processor acting as an RF modem, while the application processor runs the operating system and handles various multimedia applications.

Voice and multimedia data is received on the antenna connected to the baseband processor and this data is then packetised and sent to the application processor. The application processor either stores the multimedia content in a file system or displays/plays it in real time. But the interconnect bandwidth between the baseband and application processors can become a bottleneck in 3G/3.5G wireless mobile handsets.

Technology bandwidth requirement
Even in high-end 2G and 2.5G wireless handset designs, dual processor architectures are widely implemented. However, the data rate in these networks is usually in the range of hundreds of kbit/s, as most of the traffic is voice and simple emails and text messages. Therefore, the inter-processor communication (IPC) is usually handled by serial interfaces, like SPI, UART, or USB, which need to be available on both processors.

The data rate for 3G/3.5G wireless standards can mean a throughput of 10Mbit/s or more to support multimedia rich content and neither UART nor SPI throughput (~1Mbit/s) can satisfy this.

Although USB (full-speed) interfaces offer a theoretical bandwidth of 12Mbit/s, with protocol overhead the effective bandwidth may be less than 2Mbit/s. Moreover, as the USB host port needs to be active at all times, this translates into power consumption even when no real data is passed through the interconnect channel. Furthermore, USB’s high power consumption is another shortcoming that impacts its use as an IPC mechanism.

So none of the existing serial interfaces can provide sufficient data rates for a 3G/3.5G wireless handset. And, the limited number of available USB ports on the processors can also prevent it from being used for IPC, as USB ports are also required for PC and peripheral connections.

Since the conception of the 3G/3.5G wireless network standards, smartphone and PDA mobile handset designers have been struggling to find an efficient processor interconnect system.

Many of the designs involve using a combination of the existing serial standards, thus creating multiple data lanes that pump data from one processor to the other. Although this may seem feasible, the software that is needed to handle this type of data flow becomes extremely complicated and prone to integrity issues.

Another method is using a CPLD to interconnect the two processors. However this requires more development time, more board space, increases the overall bill of materials and is usually more power hungry.

Low-power dual-port for IPC
Low-power dual-port memory as a system interconnect implementation has recently emerged in the mobile handset space.

Dual-port memories provide high-bandwidth throughput that will be able to meet the needs of even next generation wireless data rates. At the same time as providing high effective bandwidth, dual-port memories maximise battery life by keeping consumption at a minimum compared to serial interfaces.

Interfacing across a dual-port memory is also a straightforward process and employs mechanisms that designers are already familiar with. Memory interfaces are standard interfaces that connect seamlessly to off-the-shelf processors. Additionally, no complex device drivers are required, as the ‘interface’ is memory mapped between the processors, further simplifying software development and shortening product time-to-market.

Hardware interrupts provide a simple mechanism for processor handshaking, offering substantial efficiency and minimal protocol overhead for managing the communications link when compared to interfaces such as USB. This reduced overhead also conserves power by not requiring the processors on either sides of the link to maintain a heavy/thick and cycle-hungry protocol stack that also introduces unnecessary store and load operations.

The overall efficiency of low-power dual-port IPCs has been further evaluated, as the effective throughput rather than the theoretical throughput is always the concern of handset architects and designers when evaluating IPCs.

Consider a full-speed USB interconnect implementation compared to a dual-port interface transferring a 1Mbit multimedia file from the baseband processor to the application processor.

A USB interface with an effective throughput of 2Mbit/s will take 0.5s for the file to be completely transferred. This also has the effect that both serial interfaces on both processors need to be awake for the duration of this data transfer with the relevant power consumption.

On the other hand, a low-power dual-port implemented as the processor interconnect will require only 0.02s for the 1Mb file to be transferred at 48Mbit/s. Moreover, the dual-port and the other processor can automatically go into sleep mode after the data has been transferred. This reduces the time that both processors are burning power by over 96 per cent.

Not only does a low-power dual-port interconnect provide superior performance and power consumption compared to other alternative mechanisms, it also comes in an ultra compact vfBGA package that minimises the board space requirement.

The proliferation of 3G/3.5G wireless networks, multimedia rich content, boosts the inter-processor communication bandwidth requirement of portable devices significantly. As a result, the use of conventional serial interfaces becomes insufficient and ineffective.

Low-power dual-port memory serving as an interprocessor connection not only offers high-bandwidth and low-power consumption that satisfies stringent design requirements, it also provides a range of features that can simplify software and hardware designs and, in many cases, provide the best way to handle inter-processor communication in next generation mobile handsets.

Danny Tseng is a senior applications engineer at Cypress Semiconductor, Lawrence Wong is a member of group technical staff at Texas Instruments, Hung Vuong is a senior system architect and systems and software CTO, wireless terminals, at Texas Instruments