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Friday 29 August 2008
Design
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|NewsletterEDA and IP
ESL design hit by lack of standards
Thursday 26 April 2007
Electronic System Level (ESL) design techniques are finally making the mainstream but being held back by a lack of standards.
“ESL is real, finally,” said Professor Steve Levitan, general chair of the upcoming Design Automation Conference (DAC) in the US in June. “ESL is really big and we need to go to new applications beyond boards.”
The beta version of the latest Spirit Consortium specification to allow IP blocks to be easily used in ESL design flows is due at DAC, said Ralph von Vignau, president of Spirit and a director at NXP Semiconductor, with products on the market in Q1 next year.
“The whole industry is screaming for version 1.4 and we know we are a year delayed because the OSCI standards group was a year late with their transaction level modelling specifications,” he said. “The SystemC companies are pushing for us to close on version 1.4 because it’s holding back business.”
NXP is to standardise on version 1.4 for all the IP it uses across 12 business lines. “We have created our own internal standards but we are not deploying them because we want an industry standard.”
But it is not complete. “We have had to limit ourselves with a basic version first – the hierarchy is not completely covered across all the difference views, and there are proposals for solutions to this but to put that in would take at least six months.”
Toshiba has also been researching ESL design flows for its system-on-chip developments and has shown that it cuts typical chip debug time from 130 to 41 days.
“It is about at the point where we can use behavioural synthesis to speed up designs [so that] we can use it in actual designs,” said Tohru Furuyama, general manager of the centre for Semiconductor Research and Development (CSRD) at Toshiba.
“ESL is real, finally,” said Professor Steve Levitan, general chair of the upcoming Design Automation Conference (DAC) in the US in June. “ESL is really big and we need to go to new applications beyond boards.”
The beta version of the latest Spirit Consortium specification to allow IP blocks to be easily used in ESL design flows is due at DAC, said Ralph von Vignau, president of Spirit and a director at NXP Semiconductor, with products on the market in Q1 next year.
“The whole industry is screaming for version 1.4 and we know we are a year delayed because the OSCI standards group was a year late with their transaction level modelling specifications,” he said. “The SystemC companies are pushing for us to close on version 1.4 because it’s holding back business.”
NXP is to standardise on version 1.4 for all the IP it uses across 12 business lines. “We have created our own internal standards but we are not deploying them because we want an industry standard.”
But it is not complete. “We have had to limit ourselves with a basic version first – the hierarchy is not completely covered across all the difference views, and there are proposals for solutions to this but to put that in would take at least six months.”
Toshiba has also been researching ESL design flows for its system-on-chip developments and has shown that it cuts typical chip debug time from 130 to 41 days.
“It is about at the point where we can use behavioural synthesis to speed up designs [so that] we can use it in actual designs,” said Tohru Furuyama, general manager of the centre for Semiconductor Research and Development (CSRD) at Toshiba.
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