Chipidea has developed a USB physical layer architecture using 1.8V IO devices that it claims offers the lowest power consumption for system-on-chip (SoC) designs in the 65nm and 45nm process technologies.

The USB IP supports designs with a power consumption of around 70mW. “The usage of 1.8V IO devices is an industry first,” said the company.

“This 1.8V platform extends our portfolio to a new IO device choice, while maintaining the advantages of our IP, including analogue programmability, built-in self-test (BIST) and full USB2.0 compliance,” said Celio Albuquerque, division director at Chipidea.

Fully compliant with the USB 2.0 specification, Chipidea’s 1.8V USB PHY offers D+ and D- protection to withstand transient short-circuit voltage without damage. The core also features analogue programmability for fine-tuning.